HT66F25D View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT66F25D' PDF : 177 Pages View PDF
A/D Flash Type 8-bit MCU with EEPROM
HT66F24D/HT66F25D
Bit 3
Bit 2
Bit 1
Bit 0
LTO: Low speed system oscillator ready flag
0: Not ready
1: Ready
This is the low speed system oscillator ready flag which indicates when the low speed
system oscillator is stable after power on reset or a wake-up has occurred. The flag
will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will
change to a high level after 1~2 clock cycles if the LIRC oscillator is used and 128
clock cycles if the LXT oscillator is used.
HTO: High speed system oscillator ready flag
0: Not ready
1: Ready
This is the high speed system oscillator ready flag which indicates when the high
speed system oscillator is stable. This flag is cleared to 0 by hardware when the device
is powered on and then changes to a high level after the high speed system oscillator
is stable. Therefore this flag will always be read as 1 by the application program after
device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a
wake-up has occurred, the flag will change to a high level after 128 clock cycles if the
HXT oscillator is used and after 15~16 clock cycles if the HIRC oscillator is used.
IDLEN: IDLE Mode control
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT
instruction is executed. If this bit is high, when a HALT instruction is executed the
device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running
but the system clock will continue to keep the peripheral functions operational as the
FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop
in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT
instruction is executed.
HLCLK: System clock selection
0: fH/2 ~ fH/64 or fSUB
1: fH
This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fL clock is used as the
system clock. When the bit is high the fH clock will be selected and if low the fH/2 ~
fH/64 or fL clock will be selected. When system clock switches from the fH clock to the
fL clock, the fH clock will be automatically switched off to conserve power.
CTRL Register
Bit
7
6
5
4
3
2
1
0
Name FSYSON
—
—
—
—
LVRF
LRF
WRF
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
x
0
0
Bit 7
Bit 6~3
Bit 2
FSYSON: fSYS Control in IDLE Mode
0: Disable
1: Enable
“—”: Unimplemented, read as 0
LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This
bit can only be cleared to 0 by the application program.
Rev. 1.10
43
March 25, 2013
Share Link: 
