ICS1893CY-10LF View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS1893CY-10LF' PDF : 143 Pages View PDF
ICS1893CY-10 Data Sheet - Release
Chapter 8 Pin Diagram, Listings, and Descriptions
Table 8-3. PHY Address and LED Pins
Pin
Name
P1CL
Pin
Number
59
Pin
Type
Input or
Output
Pin Description
PHY (Address Bit) 1 / Collision LED.
For more information on this pin, see Section 5.5, “Twisted-Pair Interface”.
• This multi-function configuration pin is:
– An input pin during either a power-on reset or a hardware reset. In
this case, this pin configures the ICS1893CY-10 when it is in either
hardware mode or software mode.
– An output pin following reset. In this case, this pin provides collision
status for the ICS1893CY-10.
As an input pin:
• This pin establishes the address for the ICS1893CY-10. When the
signal on this pin is logic:
– Low, that address bit is set to logic zero.
– High, that address bit is set to logic one.
P2LI
As an output pin:
• When the signal on this pin is:
– De-asserted, this state indicates the ICS1893CY-10 does not detect
any collisions.
– Asserted, this state indicates the ICS1893CY-10 detects collisions.
• The ICS1893CY-10 asserts its Collision LED for a period of
approximately 70 msec when it detects a collision.
Caution: This pin must not float. (See the notes at Section 8.3.2,
“Multi-Function (Multiplexed) Pins: PHY Address and LED
Pins”.)
60 Input or PHY (Address Bit) 2 / Link Integrity LED.
Output For more information on this pin, see Section 5.8, “Status Interface”.
• This multi-function configuration pin is:
– An input pin during either a power-on reset or a hardware reset. In
this case, this pin configures the address of the ICS1893CY-10 when
it is in either hardware mode or software mode.
– An output pin following reset. In this case, this pin provides link status
for the ICS1893CY-10.
As an input pin:
• This pins establishes the address for the ICS1893CY-10. When the
signal on this pin is logic:
– Low, that address bit is set to logic zero.
– High, that address bit is set to logic one.
As an output pin:
• When the signal on this pin is:
– De-asserted, this state indicates the ICS1893CY-10 does not have a
link.
– Asserted, this state indicates the ICS1893CY-10 has a valid link.
Caution: This pin must not float. (See the notes at Section 8.3.2,
“Multi-Function (Multiplexed) Pins: PHY Address and LED
Pins”.)
ICS1893CY-10 Rev 1/07
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
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