ICS1893CY-10LF View Datasheet(PDF) - Integrated Circuit Systems
Part Name
Description
MFG CO.
'ICS1893CY-10LF' PDF : 143 Pages View PDF
ICS1893CY-10 Data Sheet - Release
Chapter 8 Pin Diagram, Listings, and Descriptions
Table 8-5. MAC/Repeater Interface Pins: Media Independent Interface (MII) (Continued)
Pin
Name
RXCLK
Pin
Number
38
Pin
Type
Output
Pin Description
Receive Clock.
The ICS1893CY-10 sources the RXCLK to the MAC/repeater interface.
The ICS1893CY-10 uses RXCLK to synchronize the signals on the
following pins: RXD[3:0], RXDV, and RXER. The following table contrasts
the behavior on the RXCLK pin when the mode for the ICS1893CY-10 is
either 10Base-T or 100Base-TX.
10Base-T
100Base-TX
The RXCLK frequency is 2.5
MHz.
The RXCLK frequency is 25 MHz.
The ICS1893CY-10 generates its
RXCLK from the MDI data stream
using a digital PLL. When the MDI
data stream terminates, the PLL
continues to operate,
synchronously referenced to the
last packet received.
The ICS1893CY-10 generates its
RXCLK from the MDI data stream
while there is a valid link (that is,
either data or IDLEs). In the
absence of a link, the
ICS1893CY-10 uses the REF_IN
clock to generate the RXCLK.
The ICS1893CY-10 switches
between clock sources during the
period between when its CRS is
asserted and prior to its RXDV
being asserted. While the
ICS1893CY-10 is locking onto the
incoming data stream, a clock
phase change of up to 360
degrees can occur.
While the ICS1893CY-10 is
bringing up a link, a clock phase
change of up to 360 degrees can
occur.
The RXCLK aligns once per
packet.
The RXCLK aligns once, when
the link is being established.
RXD0
RXD1
RXD2
RXD3
RXDV
Note: The signal on the RXCLK pin is conditioned by the RXTRI pin.
35
Output Receive Data 0–3.
34
• RXD0 is the least-significant bit and RXD3 is the most-significant bit of
33
the MII receive data nibble.
32
• While the ICS1893CY-10 asserts RXDV, the ICS1893CY-10 transfers
the receive data signals on the RXD0–RXD3 pins to the
MAC/Repeater Interface synchronously on the rising edges of RXCLK.
36
Output Receive Data Valid.
The ICS1893CY-10 asserts RXDV to indicate to the MAC/repeater that
data is available on the MII Receive Bus (RXD[3:0]). The ICS1893CY-10:
• Asserts RXDV after it detects and recovers the Start-of-Stream
delimiter, /J/K/. (For the timing reference, see Chapter 9.5.6, “MII /
100M Stream Interface: Synchronous Receive Timing”.)
• De-asserts RXDV after it detects either the End-of-Stream delimiter
(/T/R/) or a signal error.
Note: RXDV is synchronous with the Receive Data Clock, RXCLK.
ICS1893CY-10 Rev 1/07
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
108
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