IDT71L016L100PH View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
'IDT71L016L100PH' PDF : 8 Pages View PDF
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VDD = 2.7 to 3.6V, All Temperature Ranges)
71L016L70
Symbol
Read Cycle
tRC
Parameter
Read Cycle Time
Min. Max.
70
—
tAA
Address Access Time
—
70
tACS
tCLZ(1)
tCHZ(1)
Chip Select Access Time
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
—
70
10
—
—
25
tOE
tOLZ(1)
tOHZ(1)
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
—
35
5
—
—
25
tOH
Output Hold from Address Change
10
—
tBE
tBLZ(1)
tBHZ(1)
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
—
35
5
—
—
25
Write Cycle
tWC
Write Cycle Time
70
—
tAW
Address Valid to End of Write
65
—
tCW
Chip Select Low to End of Write
65
—
tBW
Byte Enable Low to End of Write
65
—
tAS
Address Set-up Time
0
—
tWR
Address Hold from End of Write
0
—
tWP
Write Pulse Width
55
—
tDW
Data Valid to End of Write
30
—
tDH
tOW(1)
tWHZ(1)
Data Hold Time
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
0
—
5
—
—
25
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
71L016L100
Min. Max. Units
100 — ns
— 100 ns
— 100 ns
10
— ns
—
30 ns
—
50 ns
5
— ns
—
30 ns
15
— ns
—
50 ns
5
— ns
—
30 ns
100 — ns
80
— ns
80
— ns
80
— ns
0
— ns
0
— ns
70
— ns
40
— ns
0
— ns
5
— ns
—
30 ns
3771 tbl 10
TIMING WAVEFORM OF READ CYCLE NO. 1(1,2,3)
ADDRESS
DATAOUT
tRC
tAA
tOH
PREVIOUS DATAOUT VALID
tOH
DATAOUT VALID
3771 drw 06
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
5
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