IDT71L016L100PH View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
'IDT71L016L100PH' PDF : 8 Pages View PDF
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
TIMING WAVEFORM OF READ CYCLE NO. 2(1)
tRC
ADDRESS
tAA
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tOH
OE
CS
, BHE BLE
DATAOUT
tOE
tOLZ (3)
tCLZ (3) tACS (2)
tBE (2)
tBLZ (3)
tOHZ (3)
tCHZ (3)
tBHZ (3)
DATA OUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
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TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1,2,3,5)
tWC
ADDRESS
tAW
CS
BHE , BLE
tCW (3)
tBW
tWP
tCHZ (6)
tWR
(6)
tBHZ
WE
DATAOUT
tAS
tWHZ (6)
PREVIOUS DATA VALID (4)
(6)
tOW
DATA VALID
tDW
tDH
DATAIN
DATAIN VALID
3771 drw 08
NOTES:
1. WE or (BHE and BLE) or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
3. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn
off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
6
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