IDT71L016L100PH View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
MFG CO.
'IDT71L016L100PH' PDF : 8 Pages View PDF
IDT71L016
LOW POWER 3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1,2,5)
tWC
ADDRESS
tAW
CS
BHE , BLE
WE
tAS
tCW (3)
tBW
tWP
tWR
DATAOUT
DATAIN
tDW
tDH
DATAIN VALID
3771 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 3 (BHE, BLE CONTROLLED TIMING)(1,2,5)
tWC
ADDRESS
tAW
CS
BHE, BLE
WE
tCW (3)
tAS
tBW
tWP
tWR
DATAOUT
DATAIN
tDW
tDH
DATAIN VALID
3771 drw 10
NOTES:
1. WE or (BHE and BLE) or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
3. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn
off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
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