IR3Y48A1 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'IR3Y48A1' PDF : 34 Pages View PDF
A/D Converter Circuit
The IR3Y48A1 integrates an 18 MHz 10-bit full
pipeline A/D converter (ADC).
This ADC converts following signals :
1. The signal from the CCDIN input through a CDS
and a PGA
2. The signal from the ADIN input through a PGA
at the ADIN (PGA input) mode.
3. The signal from the ADIN input at the ADIN
(ADC input) mode.
A/D CONVERSION RANGE
The analog input range of the ADC is determined
by the internal reference voltage.
The full scale of the ADC is 1.0 Vp-p (single end).
A/D CONVERTER OUTPUT CODE
(AT MODE (1) REGISTER D5 = 1)
The format of an ADC digital output is a straight
binary.
Thus, when input a zero reference voltage, the
output code is "all 0", and when input a full scale
voltage, the output code is "all 1".
CLOCK, PIPELINE DELAY, DIGITAL DATA
OUTPUT TIMING
The ADCK input is used for an A/D conversion.
The ADC input signal is sampled at the falling edge
of the ADCK input and 10-bit parallel data is output
at the rising edge of the ADCK input after 5.5
clocks of pipeline delay.
IR3Y48A1
HIGH-Z CONTROL OF ADC DIGITAL OUTPUT
ADC digital outputs become High-Z under following
conditions :
q Set the ADC output bit to "1".
[Mode (1) Register D2 = 1]
w Set the SYBYN pin to low.
e Set the power control bit to "1".
[Mode (1) Register D0 = 1]
ADC Data Output (Coding : Straight Binary)
A/D INPUT
DIGITAL OUTPUT CODE
MSB
LSB
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Full scale
1111111111
:
:
:
1000000000
:
0111111111
:
:
Zero scale
0000000000
12
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