IR3Y48A1 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'IR3Y48A1' PDF : 34 Pages View PDF
Power Control
Usually, make the power control register (Mode (1)
Register D3) "1" to select low power mode.
The default setting of this register is "1".
Data Output Clock
The ADCK input or the OUTCK input is selectable
as an ADC data output clock.
General Notice for Power Supply
It is recommended to supply power to both AVDD
and DVDD from a single regulator.
(Keep the absolute maximum rating; DVDD ≤
(AVDD + 0.3 V) even at the power-up or the power-
down sequence.)
Refer to "APPLICATION CIRCUIT EXAMPLE" for
power supply decouplings.
IR3Y48A1
Serial Interface Circuit
The internal registers of IR3Y48A1 are controlled
by the 3-wire serial interface. The data is a 16-bit-
length serial data that consists of a 2-bit operation
code, a 4-bit address, and a 10-bit data. The each
bit is fetched at the rising edge of the SCK input
and the data is executed at the rising edge of the
CSN input. When not access, make the CSN input
high.
It is prohibited to write to a non-defined address.
When a data length is below 16-bit, the data is not
executed.
CSN
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SDATA
O0 O1 A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
Op
Code
Address
Data
Op code is always ineffective (don't care).
Serial Interface Write Control
15
Share Link: 
