IR3Y48A1 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'IR3Y48A1' PDF : 34 Pages View PDF
POWER DOWN MODE
The power down mode can be set either by
register setting or STBYN pin.
If one of them is set, the IR3Y48A1 powers down.
("OR" logic)
MONITOR OUTPUT
By setting the register [Mode (2) Register D1 & D0],
the signal from MONOUT is selectable. Alternatives
IR3Y48A1
are OFF, CDS output, PGA output, or REFIN/
CCDIN output. Note that the gain of the MONOUT
pin is fixed to 0 dB regardless the setting of gain
control register when the CDS output is selected.
The output level of MONOUT is shown below. The
MONOUT level becomes VCOM at zero reference
level. The signals are output in reverse for the CCD
input.
CCD
V0 = No signal
V1
V2
V3
V1'
MONOUT
V0 = No signal level
Monitor reference level = VCOM
V3'
V2'
Monitor Output Level
POLARITY INVERSION
The following input polarities can be inverted by
register setting :
q ADCK (A/D converter sampling clock)
[Mode (1) Register D6]
w SHR and SHD (CDS sampling clock)
[Mode (2) Register D3 & D2]
e BLK, OBP, CCDCLP and ADCLP (Enable controls)
[Mode (2) Register D3 & D2]
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