IR3Y48A1 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'IR3Y48A1' PDF : 34 Pages View PDF
Miscellaneous Functions
ADC DIRECT INPUT (ADIN MODE)
The direct input path to the ADC or the PGA
becomes available by register setting. The
selectable paths are shown below :
1. Function disable (default)
[Mode (1) Register D5 = 0, D4 = 0]
IR3Y48A1
2. ADIN input to the PGA
[Mode (1) Register D5 = 0, D4 = 1]
3. ADIN input to the ADC
[Mode (1) Register D5 = 1, D4 = don't care]
At the ADIN mode, the BLK, SHD and SHR inputs
are ignored.
ADIN
(N) (N + 1) (N + 2)
ADCK
ADCLP
(When ADCK is inverted,
signal (N) is sampled by this edge.)
Black Cancel
& Clamp
DO0-DO9
N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N
NOTE : This figure shows the timing when an OUTCK input function is disabled (Mode (1) D8 = 0). When it is enabled (D8
= 1), the data is output at the rising (D7 = 0) or the falling (D7 = 1) edge of the OUTCK input.
When ADCLP input is low, both black level cancel and clamp are active at the PGA input mode, and only the
clamp is active at ADC input mode.
ADIN Signal Processing (PGA Input)
The operation at ADC direct input is shown below.
Thus, the clamped level at the ADCLP timing
becomes a reference (CLPCAP at the figure
below), and the ADIN input dynamic range is +1.0
V (TYP.) from the reference level.
ADIN
ADCLP
Clamp ON
Full Scale
Zero Scale
ADIN Signal Input Level
13
CLPCAP + 1.0 V
ADC
Dynamic Range
= 1.0 Vp-p
CLPCAP
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