IR3Y48A1 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'IR3Y48A1' PDF : 34 Pages View PDF
IR3Y48A1
4. Register operations
DOUT timing control
OUTCK polarity
ADCK polarity
ADIN connection
Power control
ADC output
Black level reset
Power down
CONTROLS
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
OPERATIONS
0
DOUT synchronizes to ADCK
1
DOUT synchronizes to OUTCK
0
DOUT changes at OUTCK rising edge
1
DOUT changes at OUTCK falling edge
0
Normal operation as timing chart
1
ADCK clock inversion
00
ADIN function OFF
01
ADIN signal to PGA
1X
ADIN signal to ADC
0
Not recommended
1
Low power
0
Normal operation [ADC data output]
1
ADC output High-Z [or logic of STBYN]
0 Normal operation
1 Black level reset [or logic of RESETN]
0 Normal operation
NOTE
1
1
2
3
4
1 Power down [or logic of STBYN]
NOTES :
1. DOUT edge control is effective when D8 = 1 (DOUT
synchronizes to OUTCK).
2. Power control bit (D3) must be "1" to operate as
specified value.
The default value is "1" (low power).
3. ADC output is set to high impedance if one of the
following case is true.
Case 1 : Set "ADC output" bit to "1".
Case 2 : Set STBYN pin to low.
Case 3 : Set "Power down" bit to "1".
X : Don't care
4. Black level integral CAP [OBCAP] is discharged if the
following case is true.
Case 1 : Set "Black level reset" bit to "1".
Case 2 : Set RESETN pin to low.
17
Share Link: 
