KSZ8895FLXC View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
KSZ8895FLXC
Microchip Technology
'KSZ8895FLXC' PDF : 108 Pages View PDF
KSZ8895MQX/RQX/FQX/MLX
TABLE 3-6: PORT 5 MAC5 SW5-RMII CONNECTION (CONTINUED)
SW5-RMII MAC-to-MAC Connection
(PHY Mode)
External
MAC
Signal
(Note 3-1)
SW Signal
Type
Description
SW5-RMII MAC-to-PHY Connection
(MAC Mode)
External
PHY
Signal
(Note 3-1)
SW Signal
Type
—
Note 3-1
SMTXC/
SMREFCLK
Input (clock
comes from
SMRXC in
clock mode or
external clock
in normal
mode)
Reference Clock
REF_CLK
SMRXC
Output (Clock
mode with 50
MHz); Normal
mode w/o
connection
MAC/PHY mode in RMII is different from MAC/PHY mode in MII. There is no strap pin and register
configuration request in RMII; just follow the signal connections in the table.
3.4.19 SNI INTERFACE OPERATION
The serial network interface (SNI) is compatible with some controllers used for network layer protocol processing. This
interface can be directly connected to these types of devices. The signals are divided into two groups, one for transmis-
sion and the other for reception. The signals involved are described in Table 3-7.
TABLE 3-7: SNI SIGNALS
SNI Signal
Description
KSZ8895MQX/RQX/FQX/MLX Signal
TXEN
TXD
TXC
COL
CRS
RXD
RXC
Transmit Enable
Serial Transmit Data
Transmit Clock
Collision Detection
Carrier Sense
Serial Receive Data
Receive Clock
SMTXEN
SMTXD[0]
SMTXC
SCOL
SMRXDV
SMRXD[0]
SMRXC
This interface is a bit-wide data interface, so it runs at the network bit rate (not encoded). An additional signal on the
transmit side indicates when data is valid. Likewise, the receive side has an indicator that shows when the data is valid.
For half-duplex operation there is a signal that indicates a collision has occurred during transmission.
3.5 Advanced Functionality
3.5.1 QOS PRIORITY SUPPORT
The KSZ8895MQX/RQX/FQX/MLX provides Quality of Service (QoS) for applications such as VoIP and video confer-
encing. The KSZ8895MQX/RQX/FQX/MLX offers one, two, or four priority queues per port by setting the Registers port
control 9 bit 1 and the Registers port control 0 bit 0, the 1/2/4 queues split as follows:
• [Registers port control 9 bit 1, control 0 bit 0] = 00 single output queue as default.
• [Registers port control 9 bit 1, control 0 bit 0] = 01 egress port can be split into two priority transmit queues.
• [Registers port control 9 bit 1, control 0 bit 0] = 10 egress port can be split into four priority transmit queues.
The four priority transmit queue is a new feature in the KSZ8895MQX/RQX/FQX/MLX. The queue 3 is the highest pri-
ority queue and queue 0 is the lowest priority queue. The port Registers xxx control 9 bit 1 and the Registers port control
0 bit 0 are used to enable split transmit queues for ports 1, 2, 3, 4 and 5, respectively. If a port's transmit queue is not
split, high priority and low priority packets have equal priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or to use programmable weighted fair
queuing for the four priority queue scale by the Registers Port Control 10, 11, 12 and 13 (default value are 8, 4, 2, 1 by
their bit [6:0].
Register 130 bit [7:6] Prio_2Q[1:0] is used when the 2 Queue configuration is selected, these bits are used to map the
2-bit result of IEEE 802.1p from the Registers 128, 129 or TOS/DiffServ mapping from Registers 144-159 (for 4 Queues)
into two-queue mode with priority high or low.
2016 Microchip Technology Inc.
DS00002246A-page 35
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