KSZ8895FLXC View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
KSZ8895FLXC
Microchip Technology
'KSZ8895FLXC' PDF : 108 Pages View PDF
KSZ8895MQX/RQX/FQX/MLX
3.5.1.3 DiffServ-Based Priority
DiffServ-based priority uses the ToS Registers (Registers 144 to 159) in the Advanced Control Registers section. The
ToS priority control registers implement a fully decoded, 128-bit Differentiated Services Code Point (DSCP) register to
determine packet priority from the 6-bit ToS field in the IP header. When the most significant six bits of the ToS field are
fully decoded, 64 code points for DSCP result. These are compared with the corresponding bits in the DSCP register to
determine priority.
3.5.2 SPANNING TREE SUPPORT
Port 5 is the designated port for spanning tree support.
The other ports (Port 1 - Port 4) can be configured in one of the five spanning tree states via “transmit enable,” “receive
enable,” and “learning disable” register settings in Registers 18, 34, 50, and 66 for Ports 1, 2, 3, and 4, respectively. The
following description shows the port setting and software actions taken for each of the five spanning tree states.
Disable state: the port should not forward or receive any packets. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
Software action: the processor should not send any packets to the port. The switch may still send specific packets to
the processor (packets that match some entries in the static table with “overriding bit” set) and the processor should
discard those packets. Note: the processor is connected to Port 5 via MII interface. Address learning is disabled on the
port in this state.
Blocking state: only packets to the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1"
Software action: the processor should not send any packets to the port(s) in this state. The processor should program
the “Static MAC table” with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should also be
set so that the switch will forward those specific packets to the processor. Address learning is disabled on the port in
this state.
Listening state: only packets to and from the processor are forwarded. Learning is disabled.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g. BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see the Tail Tagging Mode section for details. Address learning
is disabled on the port in this state.
Learning state: only packets to and from the processor are forwarded. Learning is enabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see the Tail Tagging Mode section for details. Address learning
is enabled on the port in this state.
Forwarding state: packets are forwarded and received normally. Learning is enabled.
Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see the Tail Tagging Mode section for details. Address learning
is enabled on the port in this state.
3.5.3 RAPID SPANNING TREE SUPPORT
There are three operational states of the Discarding, Learning, and Forwarding assigned to each port for RSTP:
Discarding ports Do not participate in the active topology and do not learn MAC addresses.
Discarding state: the state includes three states of the disable, blocking, and listening of STP.
Port setting: "transmit enable = 0, receive enable = 0, learning disable = 1."
2016 Microchip Technology Inc.
DS00002246A-page 37
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