KSZ8895FLXC View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
KSZ8895FLXC
Microchip Technology
'KSZ8895FLXC' PDF : 108 Pages View PDF
KSZ8895MQX/RQX/FQX/MLX
Software action: the processor should not send any packets to the port. The switch may still send specific packets to
the processor (packets that match some entries in the static table with “overriding bit” set) and the processor should
discard those packets. When disabling the port’s learning capability (learning disable = ‘1’), set the Register 1 bit 5 and
bit 4 will flush rapidly with the port related entries in the dynamic MAC table and static MAC table.
Note: processor is connected to Port 5 via MII interface. Address learning is disabled on the port in this state.
Ports in Learning states learn MAC addresses, but do not forward user traffic.
Learning state: only packets to and from the processor are forwarded. Learning is enabled.
Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see the Tail Tagging Mode section for details. Address learning
is enabled on the port in this state.
Ports in Forwarding states fully participate in both data forwarding and MAC learning.
Forwarding state: packets are forwarded and received normally. Learning is enabled.
Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.”
Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU
packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The
processor may send packets to the port(s) in this state, see the Tail Tagging Mode section for details. Address learning
is enabled on the port in this state.
RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP Configuration BPDUs with the excep-
tion of a type field set to “version 2” for RSTP and “version 0” for STP, and a flag field carrying additional information.
3.5.4 TAIL TAGGING MODE
The Tail Tag is only seen and used by the Port 5 interface, which should be connected to a processor by SW5-MII/RMII
interface. The one byte tail tagging is used to indicate the source/destination port in Port 5. Only bit [3-0] are used for
the destination in the tail tagging byte. Other bits are not used. The Tail Tag feature is enabled by setting Register 12 bit
1.
FIGURE 3-9:
TAIL TAG FRAME FORMAT
TABLE 3-8: TAIL TAG RULES
Ingress to Port 5 (Host to KSZ8895MQX/RQX/FQX/MLX)
Bit [3:0]
0,0,0,0
0,0,0,1
0,0,1,0
0,1,0,0
1,0,0,0
1,1,1,1
Bit [7:4]
0,0,0,0
0,0,0,1
0,0,1,0
Destination
Reserved
Port 1 (direct forward to port 1)
Port 2 (direct forward to port 2)
Port 3 (direct forward to port 3)
Port 4 (direct forward to port 4)
Port 1, 2, 3, and 4 (direct forward to ports 1, 2, 3, and 4)
—
Queue 0 is used at destination port
Queue 1 is used at destination port
Queue 2 is used at destination port
DS00002246A-page 38
2016 Microchip Technology Inc.
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