LH28F016SCH-L View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F016SCH-L' PDF : 44 Pages View PDF
LH28F016SC-L/SCH-L
6.2.5 AC CHARACTERISTICS - WRITE OPERATION (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C or –40 to +85˚C
VERSIONS
SYMBOL
PARAMETER
tAVAV Write Cycle Time
tPHWL RP# High Recovery to WE# Going Low
tELWL CE# Setup to WE# Going Low
tWLWH WE# Pulse Width
tAVWH Address Setup to WE# Going High
tDVWH Data Setup to WE# Going High
tWHDX Data Hold from WE# High
tWHAX Address Hold from WE# High
tWHEH CE# Hold from WE# High
tWHWL WE# Pulse Width High
tWHGL Write Recovery before Read
NOTE
2
3
3
LH28F016SC-L95
LH28F016SCH-L95
MIN.
MAX.
150
1
10
50
50
50
5
5
10
30
0
LH28F016SC-L12
LH28F016SCH-L12
MIN.
MAX.
170
1
10
50
50
50
5
5
10
30
0
UNIT
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
• VCC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C
SYMBOL
VERSIONS
PARAMETER
LH28F016SC-L95
LH28F016SCH-L95
NOTE MIN.
MAX.
LH28F016SC-L12
LH28F016SCH-L12 UNIT
MIN.
MAX.
tAVAV Write Cycle Time
tPHWL RP# High Recovery to WE# Going Low
120
2
1
150
ns
1
µs
tELWL CE# Setup to WE# Going Low
tWLWH WE# Pulse Width
10
10
ns
50
50
ns
tPHHWH RP# VHH Setup to WE# Going High
2
100
100
ns
tVPWH VPP Setup to WE# Going High
2
100
100
ns
tAVWH Address Setup to WE# Going High
3
50
50
ns
tDVWH Data Setup to WE# Going High
3
50
50
ns
tWHDX Data Hold from WE# High
5
5
ns
tWHAX Address Hold from WE# High
5
5
ns
tWHEH CE# Hold from WE# High
10
10
ns
tWHWL WE# Pulse Width High
30
30
ns
tWHRL WE# High to RY/BY# Going Low
100
100 ns
tWHGL Write Recovery before Read
0
0
ns
tQVVL VPP Hold from Valid SRD, RY/BY# High
2, 4
0
tQVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4
0
0
ns
0
ns
NOTES :
1. Read timing characteristics during block erase, byte write
and lock-bit configuration operations are the same as
during read-only operations. Refer to Section 6.2.4 "AC
CHARACTERISTICS" for read-only operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN and DIN for block erase,
byte write, or lock-bit configuration.
4. VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase,
byte write, or lock-bit configuration success (SR.1/3/4/5 = 0).
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