LH28F016SCH-L View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F016SCH-L' PDF : 44 Pages View PDF
LH28F016SC-L/SCH-L
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (NOTE 1)
• VCC = 2.7 to 3.6 V, TA = 0 to +70˚C or –40 to +85˚C
VERSIONS
SYMBOL
PARAMETER
tAVAV Write Cycle Time
tPHEL RP# High Recovery to CE# Going Low
tWLEL WE# Setup to CE# Going Low
tELEH CE# Pulse Width
tAVEH Address Setup to CE# Going High
tDVEH Data Setup to CE# Going High
tEHDX Data Hold from CE# High
tEHAX Address Hold from CE# High
tEHWH WE# Hold from CE# High
tEHEL CE# Pulse Width High
tEHGL Write Recovery before Read
NOTE
2
3
3
LH28F016SC-L95
LH28F016SCH-L95
MIN.
MAX.
150
1
0
70
50
50
5
5
0
25
0
LH28F016SC-L12
LH28F016SCH-L12 UNIT
MIN.
MAX.
170
ns
1
µs
0
ns
70
ns
50
ns
50
ns
5
ns
5
ns
0
ns
25
ns
0
ns
• VCC = 3.3±0.3 V, TA = 0 to +70˚C or –40 to +85˚C
VERSIONS
LH28F016SC-L95 LH28F016SC-L12
LH28F016SCH-L95 LH28F016SCH-L12 UNIT
SYMBOL
PARAMETER
NOTE MIN.
MAX.
MIN.
MAX.
tAVAV Write Cycle Time
120
150
ns
tPHEL RP# High Recovery to CE# Going Low
2
1
1
µs
tWLEL WE# Setup to CE# Going Low
0
0
ns
tELEH CE# Pulse Width
70
70
ns
tPHHEH RP# VHH Setup to CE# Going High
2
100
100
ns
tVPEH VPP Setup to CE# Going High
2
100
100
ns
tAVEH Address Setup to CE# Going High
3
50
50
ns
tDVEH Data Setup to CE# Going High
3
50
50
ns
tEHDX Data Hold from CE# High
5
5
ns
tEHAX Address Hold from CE# High
5
5
ns
tEHWH WE# Hold from CE# High
0
0
ns
tEHEL CE# Pulse Width High
25
25
ns
tEHRL CE# High to RY/BY# Going Low
100
100 ns
tEHGL Write Recovery before Read
0
0
ns
tQVVL VPP Hold from Valid SRD, RY/BY# High
2, 4
0
0
ns
tQVPH RP# VHH Hold from Valid SRD, RY/BY# High 2, 4
0
0
ns
NOTES :
1. In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold,
and inactive WE# times should be measured relative to
the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN and DIN for block erase,
byte write, or lock-bit configuration.
4. VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase,
byte write, or lock-bit configuration success (SR.1/3/4/5 = 0).
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