LH28F016SCH-L View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F016SCH-L' PDF : 44 Pages View PDF
LH28F016SC-L/SCH-L
6.2.6 ALTERNATIVE CE#-CONTROLLED WRITES (contd.) (NOTE 1)
• VCC = 5.0±0.25 V, 5.0±0.5 V, TA = 0 to +70˚C or –40 to +85˚C
VERSIONS
(NOTE 5)
VCC±0.25 V LH28F016SC-L95
LH28F016SCH-L95
VCC±0.5 V
(NOTE 6)
(NOTE 6)
UNIT
LH28F016SC-L95 LH28F016SC-L12
LH28F016SCH-L95 LH28F016SCH-L12
SYMBOL
PARAMETER
NOTE MIN. MAX. MIN. MAX. MIN. MAX.
tAVAV
tPHEL
Write Cycle Time
RP# High Recovery to CE#
Going Low
95
2
1
100
120
ns
1
1
µs
tWLEL WE# Setup to CE# Going Low
0
0
0
ns
tELEH CE# Pulse Width
50
50
50
ns
tPHHEH RP# VHH Setup to CE# Going High 2
100
100
100
ns
tVPEH VPP Setup to CE# Going High
2
100
100
100
ns
tAVEH Address Setup to CE# Going High 3
40
40
40
ns
tDVEH Data Setup to CE# Going High 3
40
40
40
ns
tEHDX Data Hold from CE# High
5
5
5
ns
tEHAX Address Hold from CE# High
5
5
5
ns
tEHWH WE# Hold from CE# High
0
0
0
ns
tEHEL CE# Pulse Width High
25
25
25
ns
tEHRL CE# High to RY/BY# Going Low
90
90
90 ns
tEHGL Write Recovery before Read
0
0
0
ns
VPP Hold from Valid SRD,
tQVVL
2, 4
0
0
0
ns
RY/BY# High
RP# VHH Hold from Valid SRD,
tQVPH
2, 4
0
0
0
ns
RY/BY# High
NOTES :
1. In systems where CE# defines the write pulse width
(within a longer WE# timing waveform), all setup, hold,
and inactive WE# times should be measured relative to
the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN and DIN for block erase,
byte write, or lock-bit configuration.
4. VPP should be held at VPPH1/2/3 (and if necessary RP#
should be held at VHH) until determination of block erase,
byte write, or lock-bit configuration success (SR.1/3/4/5 = 0).
5. See Fig. 10 "Transient Input/Output Reference
Waveform" and Fig. 12 "Transient Equivalent Testing
Load Circuit" (High Seed Configuration) for testing
characteristics.
6. See Fig. 11 "Transient Input/Output Reference
Waveform" and Fig. 12 "Transient Equivalent Testing
Load Circuit" (Standard Configuration) for testing
characteristics.
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