LH28F016SCH-L View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F016SCH-L' PDF : 44 Pages View PDF
LH28F016SC-L/SCH-L
6.2.7 RESET OPERATIONS
VOH
RY/BY# (R)
VOL
VIH
RP# (P)
VIL
VOH
RY/BY# (R)
VOL
VIH
RP# (P)
VIL
tPLPH
(A) Reset During Read Array Mode
tPLRH
tPLPH
(B) Reset During Block Erase, Byte Write, or Lock-Bit Configuration
2.7 V/3.3 V/5 V
VCC
VIL
VIH
RP# (P)
VIL
t235VPH
(C) RP# Rising Timing
Fig. 16 AC Waveform for Reset Operation
Reset AC Specifications (NOTE 1)
SYMBOL
PARAMETER
RP# Pulse Low Time
VCC = 2.7 to 3.6 V VCC = 3.3±0.3 V VCC = 5.0±0.5 V
NOTE MIN. MAX. MIN. MAX. MIN. MAX. UNIT
tPLPH (If RP# is tied to VCC, this
100
100
100
ns
specification is not applicable)
RP# Low to Reset during
tPLRH Block Erase, Byte Write or
2, 3
—
20
12 µs
Lock-Bit Configuration
VCC 2.7 V to RP# High
t235VPH VCC 3.0 V to RP# High
4
100
100
100
ns
VCC 4.5 V to RP# High
NOTES :
1. These specifications are valid for all product versions
3. A reset time, tPHQV, is required from the latter of RY/BY#
(packages and speeds).
or RP# going high until outputs are valid.
2. If RP# is asserted while a block erase, byte write, or
4. When the device power-up, holding RP#-low minimum
lock-bit configuration operation is not executing, the reset
100 ns is required after VCC has been in predefined
will complete within 100 ns.
range and also has been in stable there.
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