LH540245U-20 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH540245U-20' PDF : 46 Pages View PDF
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (contβd)
Table 5. Control-Register Format
COMMAND
REGISTER CODE
BITS
VALUE AFTER RESET
FLAG
AFFECTED,
EMODE = H EMODE = L
IF ANY
DESCRIPTION
NOTES
Deassertion of LD does not
L
reset the programmable-
register write pointer and
IDT-compatible addressing
of programmable registers.
read pointer.
Deassertion of LD resets
the programmable-register
write pointer and read
00
L
H
β
pointer to address Word 0,
the Programmable-Almost- Non-ambiguous
H
Empty-Flag-Offset Register. addressing of
The change takes effect
programmable registers.
after a valid write operation
or a valid read operation,
respectively, to the memory
array.
L
01
L
H
Set by βRCLK, reset by
Asynchronous flag
H
PAE
βWCLK.
clocking.
Set and reset by βRCLK.
Synchronous flag clocking.
LL
Set by βWCLK, reset by
βRCLK.
Asynchronous flag
clocking.
03, 02
LH
LL
HH
HF
Set and reset by βRCLK.
Synchronous flag clocking
at output port.
HL,
HH
Set and reset by βWCLK.
Synchronous flag clocking
at input port.
L
04
L
H
Set by βWCLK, reset by
Asynchronous flag
H
PAF
βRCLK.
clocking.
Set and reset by βWCLK.
Synchronous flag clocking.
OE has no effect on an
Allows the read-address
L
internal read operation,
apart from disabling the
pointer to advance even
when Q0 β Q17 are not
outputs.
driving the output bus.
05
L
H
β
Deassertion of OE inhibits Inhibits the read-address
a read operation; whenever pointer from advancing
H
the data outputs Q0 β Q17
are in the high-Z state, the
when Q0 β Q17 are not
driving the output bus;
read pointer does not
thus, guards against data
advance.
loss.
L
Future use to control depth
06
L
H
L
β
Reserved.
cascading and interlocked
paralleling.
11, 10,
09, 08, 07
LLLLL
LLLLL
LLLLL
β
Reserved.
Reserved.
NOTES:
1. When EMODE is HIGH, and Control Register bits 00-05 are LOW, the FIFO behaves in a manner functionally equivalent to the
IDT72235B/45B FIFO of similar depth and speed grade. Under these conditions, the Control Register is not visible or accessible to the ex-
ternal system which includes the FIFO.
2. If EMODE is not asserted (is HIGH), Control Register bits 00-05 remain LOW after a reset operation. However, if EMODE is asserted (is
LOW) during a reset operation, Control Register bits 00-05 are forced HIGH, and remain HIGH until changed. Control Register bits
06-11 are unaffected by EMODE.
BOLD ITALIC = Enhanced Operating Mode
13
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