LH540245U-20 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH540245U-20' PDF : 46 Pages View PDF
2048 x 18/4096 x 18 Synchronous FIFOs
LH540235/45
DESCRIPTION OF SIGNALS AND
OPERATING SEQUENCES (cont’d)
READ CLOCK (RCLK)
A rising edge (LOW-to-HIGH transition) of RCLK initi-
ates a FIFO read cycle if LD is HIGH, or a programma-
ble-register read cycle if LD is LOW. All output-side
synchronous control inputs must meet setup and hold
times with respect to the rising edge of RCLK. The 18 data
outputs, and the output-side status flags, are meaningful
after specified time intervals, following a rising edge of
RCLK.
Conceptually, the RCLK input receives a free-running,
periodic ‘clock’ waveform, which is used to control other
signals which are edge-sensitive. However, there actually
is not any absolute requirement that the RCLK waveform
must be periodic. An ‘asynchronous’ mode of operation
is in fact possible, if REN is continuously asserted (that
is, is continuously held LOW), and RCLK receives aperi-
odic ‘clock’ pulses of suitable duration. There likewise is
no requirement that RCLK must have any particular
synchronization relation to the write clock WCLK. These
two clock inputs may in fact receive the same ‘clock’
signal; or they may receive totally-different signals, which
are not synchronized to each other in any way.
READ ENABLE (REN)
Whenever REN is being asserted (is LOW), and the
FIFO is not empty, an 18-bit data word is loaded into the
output register from the memory array at every RCLK
rising edge (LOW-to-HIGH transition). Data words are
read from the two-port memory array sequentially, regard-
less of any ongoing write operation. Whenever REN is
not being asserted (is HIGH), the output register retains
whatever data word it contained previously, and no new
data word gets loaded into it from the memory array.
To prevent underrunning the internal FIFO boundaries,
further read operations are inhibited whenever the Empty
Flag (EF) is being asserted (is LOW). If a valid write
operation then occurs, upon the completion of that write
cycle EF again goes HIGH after a time tREF, and another
read operation is allowed to begin whenever RCLK
makes another LOW-to-HIGH transition. Effectively, REN
is overridden by EF; thus, during normal FIFO operation,
REN has no effect when the FIFO is empty.
In the Enhanced Operating Mode, one (or, some-
times two) additional read-enable inputs may be
ANDed with REN to control reading, depending on
the state of Control-Register bit 05. The additional
read-enable input(s) are REN2 (and OE).
Also in the Enhanced Operating Mode, RXI/REN2
functions as REN2, an additional duplicate (albeit
assertive-HIGH) Read-Enable input, in order to pro-
vide an ‘interlocking’ mechanism for reliable
synchronization of two paralleled FIFOs.
Also, if Control Register bit 05 is HIGH, OE takes
on the extra role of serving as yet another duplicate
read-enable input, in addition to its usual function of
controlling the FIFO’s data outputs, in order to inhibit
further read operations whenever the FIFO’s data
outputs are disabled, and thereby to prevent data
loss under some circumstances.
OUTPUT ENABLE (OE)
OE is an assertive-LOW, asynchronous, output
enable. In the IDT-Compatible Operating Mode, OE has
only the effect of enabling or disabling the data outputs
Q0 – Q17. That is, disabling Q0 – Q17 does not inhibit a
read operation, for data being transmitted to the output
register; the same data will remain available later, when
the outputs are again enabled, unless subsequently over-
written. When Q0 – Q17 are enabled, each of these 18
data outputs is in a normal HIGH or LOW state, according
to the bit pattern of the data word in the output register.
When Q0 – Q17 are disabled, each of these outputs is in
the high-Z (high-impedance) state.
In the Enhanced Operating Mode, if Control Reg-
ister bit 05 is HIGH, OE behaves as an additional
read-enable control input, as well as enabling and
disabling the data outputs Q0 – Q17. Under these
circumstances, incrementing the read-address
pointer is inhibited whenever Q0 – Q17 are in the
high-Z state. Thus, ‘reading’ successive words which
fail ever to reach the outputs is prevented, as a
safeguard against data loss.
LOAD (LD)
The Sharp LH540235/45 FIFOs contain three 18-bit
programmable registers. The contents of these three
registers may be loaded with data from the data inputs
D0 – D17, or read out onto the data outputs Q0 – Q17. The
first two registers are the Programmable-Flag-Offset-
Value Registers, for the Programmable Almost-Empty
Flag (PAE) and the Programmable Almost-Full Flag (PAF)
respectively. The third register is the Control Register,
which includes several configuration-control bits
for selectively enabling and disabling Sharp’s
Enhanced-Operating-Mode features.
BOLD ITALIC = Enhanced Operating Mode
15
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