LH540245U-20 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH540245U-20' PDF : 46 Pages View PDF
LH540235/45
2048 x 18/4096 x 18 Synchronous FIFOs
WORD 0
17
3
PROGRAMMABLE-ALMOST-EMPTY-FLAG-OFFSET VALUE 1, 2
12 11 10
0
WORD 1
3
PROGRAMMABLE-ALMOST-FULL-FLAG-OFFSET VALUE 1, 2
17
12 11 10
0
WORD 2
Reserved for
future use.
CONTROL REGISTER 4, 5
6
5
4
32
17
12 11
7
6
5
43
2
CONTROL-REGISTER BITS:
6 Future use to control depth cascading and interlocked paralleling.
5 Enables suppressing reading whenever data outputs are disabled.
4 Makes PAF synchronous.
3 2 Makes HF synchronous. (See the Control-Register Format
table for the encoding of bits 02-03.)
See Table 5 for a
more complete
description of these
effects.
1 Makes PAE synchronous.
0 Selects reinitialized addressing of the programmable registers.
NOTES:
1. Default offset values all are 12710 = 7F16.
2. Bits 11-17 (LH540235) or bits 12-17 (LH540245) of both offset-value registers should
in all cases be programmed LOW (zero).
3. This bit position is used for offset values in the LH540245 only. In the LH540235, it
always should be programmed LOW.
4. See the Control-Register Format table for the default states of the Control Register,
for EMODE = HIGH (IDT-Compatible Operating Mode) and for EMODE = LOW (Enhanced Operating Mode).
The Control Register is not accessible or visible in IDT-Compatible Operating Mode.
5. The assertion of EMODE (LOW) forces Control Register bits 00-05 HIGH during a reset operation.
After that, these bits may be programmed at will.
= Reserved. Do not load with non-zero information.
BOLD ITALIC = Enhanced Operating Mode.
Figure 5. Programmable Registers
1
0
1
0
540235-4
None of these three registers makes use of all of its
available 18 bits. Figure 6 shows which bit positions of
each register are operational. The two Programmable-
Flag-Offset-Value Registers each contain an offset value
in bits 0-10 (LH540235) or bits 0-11 (LH540245); bits
11-17 (LH540235) or bits 12-17 (LH540245) are unused.
The default values for both offsets are 12710.
The Control Register configuration is shown in Fig-
ure 6 and in Table 5. For the Control Register, in the
IDT-Compatible Operating Mode, with EMODE deas-
serted (HIGH), the default value for all Control-Register
bits is zero (LOW). In the Enhanced Operating Mode,
with EMODE asserted (LOW), the default value for
bits 00-05 is HIGH, and the default value for bits 06-11
is LOW.
BOLD ITALIC = Enhanced Operating Mode
16
Whenever LD and WEN are simultaneously being
asserted (are both LOW), the 18-bit data word from the
data inputs D0 – D17 is written into the Programmable-
Almost-Empty-Flag-Offset-Value Register at the first ris-
ing edge (LOW-to-HIGH transition) of the write clock
(WCLK). (See Table 3.) If LD and WEN continue to be
simultaneously asserted, another 18-bit data word from
the data inputs D0 – D17 is written into the Programma-
ble-Almost-Full-Flag-Offset-Value Register at the second
rising edge of WCLK.
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