LPC47M112-MC View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC47M112-MC
SMSC -> Microchip
'LPC47M112-MC' PDF : 204 Pages View PDF
Enhanced Super I/O Controller with LPC Interface
Datasheet
REGISTER/SIGNAL
Interrupt Enable Register
Interrupt Identification Reg.
FIFO Control
Line Control Reg.
MODEM Control Reg.
Line Status Reg.
MODEM Status Reg.
TXD1, TXD2
INTRPT (RCVR errs)
INTRPT (RCVR Data Ready)
INTRPT (THRE)
OUT2B
RTSB
DTRB
OUT1B
RCVR FIFO
XMIT FIFO
Table 31 - Reset Function
RESET CONTROL
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET/Read LSR
RESET/Read RBR
RESET/ReadIIR/Write THR
RESET
RESET
RESET
RESET
RESET/
FCR1*FCR0/_FCR0
RESET/
FCR1*FCR0/_FCR0
RESET STATE
All bits low
Bit 0 is high; Bits 1 - 7 low
All bits low
All bits low
All bits low
All bits low except 5, 6 high
Bits 0 - 3 low; Bits 4 - 7 input
High
Low
Low
Low
High
High
High
High
All Bits Low
All Bits Low
REGISTER
ADDRESS*
ADDR = 0
DLAB = 0
ADDR = 0
DLAB = 0
ADDR = 1
DLAB = 0
ADDR = 2
ADDR = 2
ADDR = 3
ADDR = 4
ADDR = 5
ADDR = 6
Table 32 - Register Summary for an Individual UART Channel
REGISTER NAME
Receive Buffer Register (Read Only)
Transmitter Holding Register (Write
Only)
Interrupt Enable Register
Interrupt Ident. Register (Read Only)
FIFO Control Register (Write Only)
Line Control Register
MODEM Control Register
Line Status Register
MODEM Status Register
REGISTER
SYMBOL
RBR
THR
IER
IIR
FCR (Note 7)
LCR
MCR
LSR
MSR
BIT 0
Data Bit
(Note 1)
Data Bit 0
BIT 1
0 Data Bit 1
Data Bit 1
Enable
Received
Data
Available
Interrupt
(ERDAI)
"0" if Interrupt
Pending
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETHREI)
Interrupt ID
Bit
FIFO Enable
Word Length
Select Bit 0
(WLS0)
Data Terminal
Ready (DTR)
RCVR FIFO
Reset
Word Length
Select Bit 1
(WLS1)
Request to
Send (RTS)
Data Ready Overrun Error
(DR)
(OE)
Delta Clear to Delta Data
Send (DCTS) Set Ready
(DDSR)
SMSC DS – LPC47M112
Page 72
DATASHEET
Rev. 02-16-07
Share Link: 