LPC47M112-MC View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC47M112-MC
SMSC -> Microchip
'LPC47M112-MC' PDF : 204 Pages View PDF
Enhanced Super I/O Controller with LPC Interface
Datasheet
17 BITS[5:0]
RESERVED (Reserved bits cannot be written and return ‘0’ when read).
Command Port
The Command port is used to transfer MPU-401 commands to the Command Controller. The Command port is write-
only (Table 38). See Section “MPU-401 Command Controller” below.
Table 38 – MPU-401 Command Port
MPU-401 I/O BASE ADDRESS+1
D7 D6
D5
D4
D3
D2
D1
D0
TYPE W
W
W
W
W
W
W
W
NAME COMMAND REGISTER
DEFAULT
n/a
Interrupt
The MPU-401 IRQ is asserted (‘1’) when either MIDI receive data or a command acknowledge byte is available to the
host in the MIDI Data register (Figure 3). The IRQ is deasserted (‘0’) when the host reads the MIDI Data port.
NOTE: If, following a host read, data is still available in the Receive FIFO, the IRQ will remain asserted (‘1’).
The IRQ is enabled when the ‘Activate’ bit in the MPU-401 configuration registers logical device block is asserted ‘1’.
If the Activate bit is deasserted ‘0’, the MPU-401 IRQ cannot be asserted (see Section “MPU-401 Configuration
Registers”).
The MPU-401 IRQ is not affected by MIDI write data, transmit-related functions or Receiver Line Status interrupts.
The factory default Sound Blaster 16 MPU-401 IRQ is 5.
MIDI_IN
MIDI RX CLOCK4
DATA READY1
IRQ3
nREAD2
MIDI RX DATA BYTE N
MIDI RX DATA BYTE N+1
FIGURE 3 - MPU-401 INTERRUPT
NOTE: IRQ remains asserted
until read FIFO is empty
Note1
Note2
Note3
Note4
DATA READY represents the Data Ready bit B0 in the UART Line Status Register.
nREAD represents host read operations from the MIDI Data register.
IRQ is the MPU-401 Host Interface IRQ shown in Figure 2. The UART Receive FIFO Threshold = 1.
MIDI RX CLOCK is the MIDI bit clock. The MIDI bit clock period is 32μs.
SMSC DS – LPC47M112
Page 79
DATASHEET
Rev. 02-16-07
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