LPC47M112-MC View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

LPC47M112-MC

Enhanced Super I/O Controller with LPC Interface / Dual Game Port Interface

SMSC -> Microchip 

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Enhanced Super I/O Controller with LPC Interface

Datasheet

REGISTER

ADDRESS*

ADDR = 7

ADDR = 0

DLAB = 1

ADDR = 1

DLAB = 1

REGISTER NAME

Scratch Register (Note 4)

Divisor Latch (LS)

Divisor Latch (MS)

REGISTER

SYMBOL

SCR

DDL

DLM

BIT 0

Bit 0

Bit 0

Bit 8

BIT 1

Bit 1

Bit 1

Bit 9

*DLAB is Bit 7 of the Line Control Register (ADDR = 3).

Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is

empty.

Table 32 - Register Summary for an Individual UART Channel (continued)

BIT 2

Data Bit 2

Data Bit 2

Enable

Receiver Line

Status

Interrupt

(ELSI)

BIT 3

Data Bit 3

Data Bit 3

Enable

MODEM

Status

Interrupt

(EMSI)

BIT 4

Data Bit 4

Data Bit 4

0

BIT 5

Data Bit 5

Data Bit 5

0

BIT 6

Data Bit 6

Data Bit 6

0

BIT 7

Data Bit 7

Data Bit 7

0

Interrupt ID Bit Interrupt ID Bit 0

(Note 5)

XMIT FIFO

Reset

Number of

Stop Bits

(STB)

OUT1

(Note 3)

Parity Error

(PE)

DMA Mode

Select (Note

6)

Parity Enable

(PEN)

Reserved

Even Parity

Select (EPS)

OUT2

(Note 3)

Framing Error

(FE)

Loop

Break

Interrupt (BI)

Trailing Edge

Ring Indicator

(TERI)

Bit 2

Bit 2

Bit 10

Delta Data

Carrier Detect

(DDCD)

Bit 3

Bit 3

Bit 11

Clear to Send

(CTS)

Bit 4

Bit 4

Bit 12

0

Reserved

Stick Parity

0

Transmitter

Holding

Register

(THRE)

Data Set

Ready (DSR)

Bit 5

Bit 5

Bit 13

FIFOs

Enabled

(Note 5)

RCVR Trigger

LSB

FIFOs

Enabled

(Note 5)

RCVR Trigger

MSB

Set Break

0

Divisor Latch

Access Bit

(DLAB)

0

Transmitter Error in RCVR

Empty (TEMT) FIFO (Note 5)

(Note 2)

Ring Indicator Data Carrier

(RI)

Detect (DCD)

Bit 6

Bit 6

Bit 14

Bit 7

Bit 7

Bit 15

Note 3: This bit no longer has a pin associated with it.

Note 4: When operating in the XT mode, this register is not available.

Note 5: These bits are always zero in the non-FIFO mode.

Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.

Note 7: The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register

(runtime register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at

offset 0x21).

SMSC DS – LPC47M112

Page 73

DATASHEET

Rev. 02-16-07

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