LPC47M112-MC View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
LPC47M112-MC
SMSC -> Microchip
'LPC47M112-MC' PDF : 204 Pages View PDF
Enhanced Super I/O Controller with LPC Interface
Datasheet
15 MPU-401 MIDI UART
15.1 Overview
Serial Port 3 is used exclusively in the LPC47M112 as an MPU-401-compatible MIDI Interface. The LPC47M112
MPU-401 hardware includes a Host Interface, an MPU-401 command controller, configuration registers, and a
compatible UART (Figure 2).
Each of these components are discussed in detail, below.
Only the MPU-401 UART (pass-through) mode is included in this implementation. MPU-401 UART mode is
supported on the Sound Blaster 16 Series-compatible MIDI hardware. The Sound Blaster 16 hardware is supported
by Microsoft Windows Operating Systems.
In MPU-401 UART mode, data is transferred without modification between the host and the MIDI device (UART).
Once UART mode is entered using the UART MODE command (3Fh), the only MPU-401 command that the interface
recognizes is RESET (FFh).
MPU-401
COMMAND
CONTROLLER
SA[15:0]
SD[7:0]
nIOW
nIOR
IRQ
HOST
INTERFACE
UART
TX
RX
MIDI_OUT
MIDI_IN
CONFIGURATION
REGISTERS
FIGURE 2 - MPU-401 MIDI INTERFACE
Note: This figure is for illustration purposes only and is not intended to suggest specific implementation details.
15.2 Host Interface
Overview
The Host Interface includes two contiguous 8-bit run-time registers (the Status/Command Port and the Data Port),
and an interrupt. For illustration purposes, the Host Interface block shown in Figure 2 uses standard ISA signaling.
Address decoding and interrupt selection for the Host Interface are determined by device configuration registers (see
Section “MPU-401Configuration Registers”).
I/O Addresses
The Sound Blaster 16 MPU-401 UART mode MIDI interface requires two consecutive I/O addresses with possible
base I/O addresses of 300h and 330h. The default is 330h. The LPC47M112 MPU-401 I/O base address is
programmable on even-byte boundaries throughout the entire I/O address range (see Section “Activate and I/O Base
address”).
SMSC DS – LPC47M112
Page 76
DATASHEET
Rev. 02-16-07
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