LRS1383 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

MFG CO.

LRS1383

Stacked Chip 32M Flash and 8M SRAM

Sharp Electronics 

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FUM00701

54

Bus

Operation

Command

Comments

Write

<First cycle>

Data=60H

Addr=Configuration Register

Code (see Table 14 or

Set Read Table 17)

Configuration

Register, <Second cycle>

Set Partition Data= 03H (Read

Configuration Configuration), or

Register 04H(Partition

Configuration)

Addr=Configuration Register

Code (see Table 14 or

Table 17)

Write

Read Status Data=70H

Register Addr=Within Partition

Read

Status Register Data

Addr=Within Partition

Standby

Check SR.4, 5

Both 1=Command Sequence

Error

Write

Read

ID

Code

Data=90H

Addr=Within

Partition

Read

Read/Partition Configuration

Register Code

Addr=0005H/0006H

(see Table 6 through

Table 8)

Standby

Check DQ15-DQ0 for Read/

Partition Configuration

Register Code

Configuration register code can be read after set read/

partition configuration register operation.

SR.5 and SR.4 are only cleared by the Clear Status

Register command.

If an error is detected, clear the status register before

attempting retry or other error recovery.

After a successful set read/partition configuration

register operation, the device returns to read array mode.

Bus

Operation

Command

Comments

Write

Read Status Data=70H

Register Addr=Within Partition

Read

Status Register Data

Addr=Within Partition

Check SR.7

Standby

1=WSM Ready

0=WSM Busy

Figure 16. Set Read Configuration Register and Set Partition Configuration Register Flowchart

Synchronous burst mode will be available for future device.

Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001

Rev. 2.20

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