LRS1383 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1383' PDF : 114 Pages View PDF
FUM00701
46
The two-cycle command sequence ensures that block is
not accidentally locked-down. An invalid Set Block
Lock-down Bit command sequence will result in both
status register bits SR.5 and SR.4 being set to "1" and the
operation will not be executed.
The Set Block Lock-down Bit command is available
when the power supply voltage is specified level,
independent of the voltage on VPP.
At power-up or device reset, since no blocks are locked-
down, write the Set Block Lock-down Bit command as
necessary.
While WP# is VIH, the lock-down bits are disabled but
not cleared. Once any block is locked-down, it cannot be
cleared until power-off or device reset.
4.15 OTP Program Command
OTP program is executed by a two-cycle command
sequence. At the first cycle, command (C0H) and an
address within the OTP block (see Figure 4) is written,
followed by the second write that specifies the address
and data. After writing the command, the device outputs
the status register data when any address within the
device is selected. The WSM then takes over, controlling
the internal OTP program algorithm. The system CPU
can detect the OTP program completion by analyzing the
output data of the status register bit SR.7. Figure 13.1 and
Figure 13.2 show OTP program flowchart.
The address written at the command cycle must be the
address within the OTP block (refer to Figure 4). Writing
an address outside the OTP block will cause a OTP
program error and the status register bit SR.4 is set to "1".
Clear the status register before writing next command.
The internal WSM verify only detects errors for "1"s that
are not successfully programmed to "0"s. Check the status
register bit SR.4 at the end of OTP program. If a OTP
program error is detected, the status register should be
cleared before system software attempts corrective
actions.
For reliable OTP program operation, apply the specified
voltage on VCC and VPPH1/2 on VPP. In the absence of this
voltage, OTP program operations are not guaranteed. For
example, attempting an OTP program at VPP VPPLK
causes SR.4 and SR.3 being set to "1". OTP program
operation on locked area causes SR.4 and SR.1 being set
to "1" and the operation will not be executed.
OTP program cannot be suspended through the (Page
Buffer) Program Suspend command (B0H). Even if the
(Page Buffer) Program Suspend command is written
during OTP program operation, the suspend command
will be ignored.
If an error is detected during the OTP program operation,
error bits for all status registers are set to "1". This
requires that the Clear Status Register command be
written to all partitions to clear the error bits.
Dual work operation is not available while the OTP
program mode, and the memory array data cannot be read
even if that operation has been completed. To return to the
read array mode, write the Read Array command (FFH)
to the partition’s CUI after the completion of the OTP
program operation.
Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001
Rev. 2.20
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