LRS1383 View Datasheet(PDF) - Sharp Electronics

Part Name

Description

MFG CO.

LRS1383

Stacked Chip 32M Flash and 8M SRAM

Sharp Electronics 

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FUM00701

45

Bus

Operation

Command

Comments

Write

Clear Block

Lock Bit

<First cycle>

Data=60H

Addr=Within Block to be

Unlocked

<Second cycle>

Data= D0H

Addr=Within Block to be

Unlocked

Read

Status Register Data

Addr=Within Partition

Standby

Check SR.4, 5

Both 1=Command Sequence

Error

Write

Read

ID

Code

Data=90H

Addr=Within

Partition

Read

Lock Bit Data

Addr=Block Address+2

(see Table 6 through

Table 8)

Standby

Check DQ0

0=Lock Bit is Cleared

Repeat for the subsequent clear block lock bit.

Lock status check can be done after each clear block lock

bit operation or after a sequence of clear block lock bit

operations.

SR.5 and SR.4 are only cleared by the Clear Status

Register command in cases where multiple block lock

bits are cleared before full status is checked.

If an error is detected, clear the status register before

attempting retry or other error recovery.

Write FFH after a sequence of clear block lock bit

operations to place device in read array mode.

Bus

Operation

Write

Read

Standby

Command

Read Status

Register

Comments

Data=70H

Addr=Within Partition

Status Register Data

Addr=Within Partition

Check SR.7

1=WSM Ready

0=WSM Busy

Figure 12. Clear Block Lock Bit Flowchart

Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001

Rev. 2.20

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