FUM00701
30
Bus
Operation
Command
Comments
Standby
Check SR.3
1=VPP Error Detect
Standby
Check SR.1
1=Device Protect Detect
All Blocks are locked.
Standby
Check SR.4,5
Both 1=Command Sequence
Error
Standby
Check SR.5
1=Full Chip Erase Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register Command in cases where multiple blocks
are erased before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
Figure 6.2. Automated Full Chip Erase Flowchart (Continued)
Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001
Rev. 2.20