LTC3717-1 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
LTC3717-1
Linear Technology
'LTC3717-1' PDF : 20 Pages View PDF
LTC3717-1
APPLICATIO S I FOR ATIO
Tying VRNG to 1.1V will set the current sense voltage range
for a nominal value of 110mV with current limit occurring
at 143mV. To check if the current limit is acceptable,
assume a junction temperature of about 40°C above a
70°C ambient with ρ110°C = 1.4:
ILIMIT
≥
143mV
(1.4)(0.010Ω)
+
1 (3.7A)
2
=
12.1A
and double check the assumed TJ in the MOSFET:
PBOT
=
2.5V – 1.25V
2.5V
(12.1A)2(1.4)(0.010Ω)
=
1.02W
TJ = 70°C + (1.02W)(40°C/W) = 111°C
Because the top MOSFET is on roughly the same amount
of time as the bottom MOSFET, the same Si4874 can be
used as the synchronous MOSFET.
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
CIN is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR of
0.013Ω to minimize output voltage changes due to induc-
tor ripple current and load steps. For current sinking
applications where current flows back to the input through
the top transistor, output capacitors with a similar amount
of bulk C and ESR should be placed on the input as well.
(This is typically the case, since VIN is derived from
another DC/DC converter.) The ripple voltage will be only:
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR)
= (4A) (0.013Ω) = 52mV
However, a 0A to 10A load step will cause an output
change of up to:
∆VOUT(STEP) = ∆ILOAD (ESR) = (10A) (0.013Ω) = 130mV
An optional 22µF ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 7.
PC Board Layout Checklist
When laying out a PC board follow one of the two sug-
gested approaches. The simple PC board layout requires
a dedicated ground plane layer. Also, for higher currents,
it is recommended to use a multilayer board to help with
heat sinking power components.
CSS
0.1µF
R3
R4
RPG
11k 39k 100k
CC1
470pF
RC
20k
CC2
100pF
CON 0.01µF
RUN/SS BOOST
PGOOD
TG
LTC3717-1
VRNG
SW
SENSE+
ITH
SGND
PGND
SENSE–
BG
VON
ION
INTVCC
DRVCC
VFB
VCC
RON
511k
(OPT)
0.1µF
VREF
EXTVCC
10Ω
CIN, COUT1-2: CORNELL DUBILIER ESRE181E04B
L1: SUMIDA CEP125-0R68MC-H
DB
CMDSH-3
CB
0.22µF
CVCC
4.7µF
RF
1Ω
CF
0.1µF
M1
Si4874
M2
Si4874
D2
B320A
L1
0.68µH
D1
B320A
CIN +
22µF
CIN VIN = 2.5V
180µF
6.3V
4V
X7R
×2 VOUT
1.25V
+ COUT1-2
270µF
±10A
COUT3
22µF
2V
6.3V
×2
X7R
VEXT 5V
37171 F07
16
Figure 7. Design Example: 1.25V/±10A at 250kHz
sn37171 37171fs
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