LTC4214 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4214' PDF : 32 Pages View PDF
LTC4214-1/LTC4214-2
APPLICATIO S I FOR ATIO
MOSFET off. To handle this situation, the TIMER dis-
charges CT slowly with a 5µA pull-down whenever the
SENSE voltage is less than 50mV. Therefore, any intermit-
tent overload with VOUT < 3V and an aggregate duty cycle
of 12.5% or more will eventually trip the circuit breaker
and shut down the LTC4214. Figure 4 shows the circuit
breaker response time in seconds normalized to 1µF for
IDRN = 0µA. The asymmetric charging and discharging of
CT is a fair gauge of MOSFET heating.
The normalized circuit response time is estimated by
[ ] t =
CT(µF)
3
(40 + 8 • IDRN) • D − 5
(4)
100
IDRN = 0µA
10
t
3
=
CT(µF) [(40 + 8 • IDRN) • D – 5]
1
0.1
0.01
0
10 20 30 40 50 60 70 80 90 100
FAULT DUTY CYCLE (%)
4214 F04
Figure 4. Circuit-Breaker Response Time
SHUTDOWN COOLING CYCLE
For the LTC4214-1 (latchoff version), TIMER latches high
with a 5µA pull-up after the circuit breaker fault TIMER
reaches 3V. For the LTC4214-2 (automatic retry version),
a shutdown cooling cycle begins if TIMER reaches the 3V
threshold. TIMER starts with a 5µA pull-down until it
reaches the 1.7V threshold. Then, the 5µA pull-up turns
back on until TIMER reaches the 3V threshold. Four 5µA
pull-down cycles and three 5µA pull-up cycles occur
between the 1.7V and 3V thresholds, creating a time
interval given by:
tSHUTDOWN
=
7
•
1.3V •
5µA
CT
(5)
At the 1.7V threshold of the last pull-down cycle, a GATE
ramp-up is attempted.
SOFT-START
Soft-start limits the inrush current profile during GATE
start-up. Unduly long soft-start intervals can exceed the
MOSFET’s SOA rating if powering up into an active load. If
SS floats, an internal current source ramps SS from 0V to
1.6V in about 220µs. Connecting an external capacitor CSS
from SS to ground modifies the ramp to approximate an
RC response of:
VSS (t)
≈
VSS
•
1−
e
−
RSS
t
•C SS
(6)
An internal resistor divider (69.35k/3.65k) scales VSS(t)
down by 20 times to give the analog current limit thresh-
old:
VACL (t)
=
VSS (t)
20
−
VOS
(7)
This allows the inrush current to be limited to VACL(t)/RS.
The offset voltage, VOS (10mV), ensures CSS is sufficiently
discharged and the ACL amplifier is in current limit before
GATE start-up. SS is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
421412f
15
Share Link: 
