LTC4214 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4214' PDF : 32 Pages View PDF
LTC4214-1/LTC4214-2
APPLICATIO S I FOR ATIO
GATE
GATE is pulled low to VEE under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out. When GATE turns
on, a 50µA current source charges the MOSFET gate and
any associated external capacitance. The gate drive is
limited to no more than VIN.
Gate-drain capacitance (CGD) feedthrough at the first
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET. A unique circuit
pulls GATE low with practically no usable voltage at VIN
and eliminates current spikes at insertion. A large external
gate-source capacitor is thus unnecessary for the purpose
of compensating CGD. Instead, a smaller value (≥ 5nF)
capacitor CC is adequate. CC also provides compensation
for the analog current limit loop.
GATE has two comparators: the GATE low comparator
looks for < 0.5V threshold prior to initial timing or a GATE
start-up cycle; the GATE high comparator looks for < 2.8V
relative to VIN and, together with the DRAIN low compara-
tor, sets PWRGD status during GATE start-up.
SENSE
The SENSE pin is monitored by the circuit breaker (CB)
comparator, the analog current limit (ACL) amplifier and
the fast current limit (FCL) comparator. Each of these three
measures the potential of SENSE relative to VEE. When
SENSE exceeds 50mV, the CB comparator activates the
40µA TIMER pull-up. At 70mV, the ACL amplifier servos
the MOSFET current and, at 200mV, the FCL comparator
abruptly pulls GATE low in an attempt to bring the MOSFET
current under control. If any of these conditions persists
long enough for TIMER to charge CT to 3V (see Equa-
tion␣ 3), the LTC4214 shuts down and pulls GATE low.
If the SENSE pin encounters a voltage greater than 70mV,
the ACL amplifier will servo GATE downwards in an
attempt to control the MOSFET current. Since GATE
overdrives the MOSFET in normal operation, the ACL
amplifier needs time to discharge GATE to the threshold
of the MOSFET. For a mild overload the ACL amplifier can
control the MOSFET current, but in the event of a severe
overload the current may overshoot. At SENSE = 200mV
the FCL comparator takes over, quickly discharging the
GATE pin to near VEE potential. FCL then releases and the
ACL amplifier takes over. All the while TIMER is running.
The effect of FCL is to add a nonlinear response to the
control loop in favor of reducing MOSFET current.
Owing to inductive effects in the system, FCL typically
overcorrects the current limit loop and GATE under-
shoots. A zero in the loop (resistor RC in series with the
gate capacitor) helps the ACL amplifier to recover.
SHORT-CIRCUIT OPERATION
Circuit behavior arising from a load side low impedance
short is shown in Figure 5 for the LTC4214. Initially, the
current overshoots the fast current limit level of VSENSE =
200mV (Trace 2) as the GATE pin works to bring VGS under
control (Trace 3). The overshoot glitches the backplane in
the negative direction and when the current is reduced to
70mV/RS, the backplane responds by glitching in the
positive direction.
SUPPLY RING
OWING TO CURRENT
OVERSHOOT
SUPPLY RING
OWING TO MOSFET
TURN-OFF
GND WITH
RESPECT TO –12V
0.1ms
10V
SENSE
0.1ms
200mV
GATE
0.1ms
10V
TIMER
0.1ms
2V
TRACE 1
ONSET OF OUTPUT
SHORT CIRCUIT
FAST
CURRENT
LIMIT
ANALOG
CURRENT
LIMIT
TRACE 2
TRACE 3
TRACE 4
CTIMER RAMP LATCH OFF
4214 F05
Figure 5. Output Short-Circuit Behavior of LTC4214
421412f
16
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