LTC4214 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4214' PDF : 32 Pages View PDF
LTC4214-1/LTC4214-2
APPLICATIO S I FOR ATIO
VIN CLEARS VLKO, CHECK UV > VUVHI, OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL
TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
12
3 4 56 7 8 9 10 11
GND – (–12V)
UV/OV
VIN
VLKO
TIMER
5µA
VTMRH
40µA + 8 • IDRN
5µA
VTMRL
5µA
GATE
SS
VGATEL
50µA
20 • (VACL + VOS)
20 • (VCB + VOS)
20 • VOS
50µA
VIN – VGATEH
SENSE
VACL
VCB
VOUT
DRAIN
VDRNCL
VDRNL
PWRGD
INITIAL TIMING
GATE
START-UP
4214 F08
Figure 8. System Power-Up Timing (All Waveforms are Referenced to VEE)
the load current. If the SENSE voltage (VSENSE – VEE)
reaches the VCB threshold at time point 7, the circuit
breaker TIMER activates. The TIMER capacitor, CT, is
charged by a (40µA + 8 • IDRN) current pull-up. As the load
capacitor nears full charge, load current begins to decline.
At time point 8, the load current falls and the SENSE
voltage drops below VACL(t). The analog current limit loop
shuts off and the GATE pin ramps further. At time point 9,
the SENSE voltage drops below VCB, the fault TIMER cycle
ends, followed by a 5µA discharge cycle (cool off). The
duration between time points 7 and 9 must be shorter than
one circuit breaker delay to avoid a fault time out during
GATE ramp-up. When GATE ramps past the VGATEH thresh-
old at time point 10, PWRGD pulls low. At time point␣ 11,
GATE reaches its maximum voltage as determined by VIN.
Live Insertion with Short Pin Control of UV/OV
In the example shown in Figure 9, power is delivered
through long connector pins whereas the UV/OV divider
makes contact through a short pin. This ensures the power
connections are firmly established before the LTC4214 is
activated. At time point 1, the power pins make contact and
VIN ramps through VLKO. At time point 2, the UV/OV divider
421412f
20
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