LTC4214 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4214' PDF : 32 Pages View PDF
LTC4214-1/LTC4214-2
APPLICATIO S I FOR ATIO
TIMER commences charging CT (Trace 4) while the analog
current limit loop maintains the fault current at 70mV/RS,
which in this case is 3.5A (Trace 2). Note that the back-
plane voltage (Trace 1) sags under load. Timer pull-up is
accelerated by VOUT. When CT reaches 3V, GATE turns off,
PWRGD pulls high, the load current drops to zero and the
backplane rings in the positive direction. The transient
associated with the GATE turn off can be controlled with a
snubber to reduce ringing and transient voltage suppres-
sor to clip off large spikes. The choice of RC for the
snubber is usually done experimentally. The value of the
snubber capacitor is usually chosen between 10 to 100
times the MOSFET COSS. The value of the snubber resistor
is typically between 3Ω to 100Ω. In many cases, a simple
short-circuit test can be performed to determine the
component values needed.
A low impedance short on one card may influence the
behavior of others sharing the same backplane. The initial
glitch and backplane sag as seen in Figure 5 Trace 1, can
rob charge from output capacitors on adjacent cards.
When the faulty card shuts down, current flows in to
refresh the capacitors. If LTC4214s are used by the other
cards, they respond by limiting the inrush current to a
value of 70mV/RS. If CT is sized correctly, the capacitors
will recharge long before CT times out.
POWER GOOD, PWRGD
PWRGD latches low if GATE charges up to within 2.8V of
VIN and DRAIN pulls below VDRNL during start-up. PWRGD
is reset in UVLO, in a UV condition or if CT charges up to
3V. An overvoltage condition has no effect on PWRGD
status. A 50µA current pulls this pin high during reset.
Various ways of using the PWRGD pin for interfacing with
a Power Module load are shown in the Typical Application
as well as Figures 2, 3, 18 and 19.
MOSFET SELECTION
The external MOSFET switch must have adequate safe
operating area (SOA) to handle short-circuit conditions
until TIMER times out. These considerations take prece-
dence over DC current ratings. A MOSFET with adequate
SOA for a given application can always handle the required
current, but the opposite may not be true. Consult the
manufacturer’s MOSFET data sheet for safe operating area
and effective transient thermal impedance curves.
MOSFET selection is a 3-step process by assuming the
absense of a soft-start capacitor. First, RS is calculated and
then the time required to charge the load capacitance is
determined. This timing, along with the maximum short-
circuit current and maximum input voltage defines an
operating point that is checked against the MOSFET’s SOA
curve.
To begin a design, first specify the required load current
and Ioad capacitance, IL and CL. The circuit breaker
current trip point (VCB/RS) should be set to accommodate
the maximum load current. Note that maximum input
current to a DC/DC converter is expected at VSUPPLY(MIN).
RS is given by:
RS
=
VCB(MIN)
IL(MAX)
(8)
where VCB(MIN) = 44mV represents the guaranteed mini-
mum circuit breaker threshold.
During the initial charging process, the LTC4214 may
operate the MOSFET in current limit, forcing (VACL) be-
tween 60mV to 80mV across RS. The minimum inrush
current is given by:
IINRUSH(MIN)=
60mV
RS
(9)
Maximum short-circuit current limit is calculated using
the maximum VSENSE. This gives
ISHORTCIRCUIT(MAX)=
80mV
RS
(10)
The TIMER capacitor CT must be selected based on the
slowest expected charging rate; otherwise TIMER might
time out before the load capacitor is fully charged. A value
421412f
17
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