LTC4214 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC4214' PDF : 32 Pages View PDF
LTC4214-1/LTC4214-2
APPLICATIO S I FOR ATIO
25
Si4864DY •
20
•
Si4876DY
15
IRF7413
Si4410DY
10
•
•
5
•• Si4412ADY
IRF7803
0
0 1000 2000 3000 4000 5000 6000 7000
MOSFET, CISS (pF)
4214 F06
Figure 6. Recommended Compensation
Capacitor CC vs MOSFET CISS
tween the compensation capacitor CC and the MOSFET’s
CISS. The line in Figure 6 is used to select a starting value
for CC based upon the MOSFET’s CISS specification. Opti-
mized values for CC are shown for several popular
MOSFETs. Differences in the optimized value of CC versus
the starting value are small. Nevertheless, compensation
values should be verified by board level short-circuit
testing.
As seen in Figure 5 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramati-
cally owing to series inductance. If this voltage avalanches
the MOSFET, current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4214’s
VEE and SENSE pins are strongly recommended. The
drawing in Figure 7 illustrates the correct way of making
connections between the LTC4214 and the sense resistor.
PCB layout should be balanced and symmetrical to mini-
mize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO –12V BACKPLANE
TRACK WIDTH W:
0.03" PER AMP W
ON 1 OZ COPPER
SENSE RESISTOR
4214 F07
TO
TO
SENSE
VEE
Figure 7. Making PCB Connections to the Sense Resistor
TIMING WAVEFORMS
System Power-Up
Figure 8 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
time point 1, the supply ramps up, together with UV/OV,
VIN, VOUT, DRAIN and PWRGD. At time point 2, VIN
exceeds VLKO and the internal logic checks for UV > VUVHI,
OV < VOVHI, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS
and TIMER < VTMRL. If all conditions are met, an initial
timing cycle starts and the TIMER capacitor is charged by
a 5µA current source pull-up. At time point 3, TIMER
reaches the VTMRH threshold and the initial timing cycle
terminates. The TIMER capacitor is quickly discharged. At
time point 4, the VTMRL threshold is reached and the
conditions of GATE < VGATEL, SENSE < VCB and
SS␣ <␣ 20␣ •␣ VOS must be satisfied before a GATE ramp-up
cycle begins. SS ramps up as dictated by RSS • CSS (as in
Equation 6); GATE is held low by the analog current limit
(ACL) amplifier until SS crosses 20 • VOS. Upon releasing
GATE, 50µA sources into the external MOSFET gate and
compensation network. When the GATE voltage reaches
the MOSFET’s threshold, current begins flowing into the
load capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
VACL(t) (Equation 7) and soft-start limits the slew rate of
421412f
19
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