LTC6945 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC6945' PDF : 28 Pages View PDF
LTC6945
OPERATION
CHARGE PUMP
The charge pump, controlled by the PFD, forces sink
(DOWN) or source (UP) current pulses onto the CP pin,
which should be connected to an appropriate loop filter.
See Figure 5 for a simplified schematic of the charge pump.
UP
CPUP
VCP+
VCP+
CPMID
+– 0.9V
–
+
THI
VCP+/2
CP
25
–
+
TLO
DOWN
CPDN
+– 0.9V
6945 F05
Figure 5. Simplified Charge Pump Schematic
The output current magnitude ICP may be set from 250μA to
11.2mA using the CP[3:0] bits found in serial port register
h09. A larger ICP can result in lower in-band noise due to
the lower impedance of the loop filter components. See
Table 5 for programming specifics and the Applications
Information section for loop filter examples.
Table 5. CP[3:0] Programming
CP[3:0]
0
1
2
3
4
5
6
7
8
9
10
11
12 to 15
ICP
250μA
350μA
500μA
700μA
1.0mA
1.4mA
2.0mA
2.8mA
4.0mA
5.6mA
8.0mA
11.2mA
Invalid
The CPINV bit found in register h0A should be set for ap-
plications requiring signal inversion from the PFD, such
as for loops using negative-slope tuning oscillators, or
12
inverting op amps in conjunction with positive-slope tuning
oscillators. A passive loop filter as shown in Figure 15,
used in conjunction with a positive-slope VCO, requires
CPINV = 0.
CHARGE PUMP FUNCTIONS
The charge pump contains additional features to aid
in system start-up and monitoring. See Table 6 for a
summary.
Table 6. CP Function Bit Descriptions
BIT
DESCRIPTION
CPCHI
Enable High Voltage Output Clamp
CPCLO
Enable Low Voltage Output Clamp
CPDN
Force Sink Current
CPINV
Invert PFD Phase
CPMID
Enable Mid-Voltage Bias
CPRST
Reset PFD
CPUP
Force Source Current
CPWIDE
Extend Current Pulse Width
THI
High Voltage Clamp Flag
TLO
Low Voltage Clamp Flag
The CPCHI and CPCLO bits found in register h0A enable
the high and low voltage clamps, respectively. When CPCHI
is enabled and the CP pin voltage exceeds approximately
VCP+ – 0.9V, the THI status flag is set, and the charge pump
sourcing current is disabled. Alternately, when CPCLO is
enabled and the CP pin voltage is less than approximately
0.9V, the TLO status flag is set, and the charge pump sinking
current is disabled. See Figure 5 for a simplified schematic.
The CPMID bit also found in register h0A enables a
resistive VCP+/2 output bias which may be used to pre-
bias troublesome loop filters into a valid voltage range
before attempting to lock the loop. When using CPMID,
it is recommended to also assert the CPRST bit, forcing
a PFD reset. Both CPMID and CPRST must be set to “0”
for normal operation.
The CPUP and CPDN bits force a constant ICP source or
sink current, respectively, on the CP pin. The CPRST bit
may also be used in conjunction with the CPUP and CPDN
bits, allowing a pre-charge of the loop to a known state,
if required. CPUP, CPDN, and CPRST must be set to “0”
to allow the loop to lock.
6945f
Share Link: 
