LTC6945
OPERATION
MASTER–CS
MASTER–SDI
Addr0 + Wr
Byte 0
Byte 1
Byte 2
Hi-Z
LTC6945–SDO
6945 F12
Figure 13. Serial Port Auto-Increment Write
MASTER–CS
MASTER–SDI
Addr0 + Rd
DON’T CARE
Hi-Z
LTC6945–SDO
Byte 0
Byte 1
Byte 2
Hi-Z
6945 F13
Figure 14. Serial Port Auto-Increment Read
Serial Port Registers
The memory map of the LTC6945 may be found in Table 8,
with detailed bit descriptions found in Table 9. The register
address shown in hexadecimal format under the ADDR
column is used to specify each register. Each register is
denoted as either read-only (R) or read-write (R/W). The
register’s default value on device power-up or after a reset
is shown at the right.
The read-only register at address h00 is used to determine
different status flags. These flags may be instantly output
on the STAT pin by configuring register h01. See the STAT
Output section for more information.
The read-only register at address h0B is a ROM byte for
device identification.
STAT Output
The STAT output pin is configured with the x[5:0] bits
of register h01. These bits are used to bit-wise mask, or
enable, the corresponding status flags of status register
h00, according to Equation 1. The result of this bit-wise
Boolean operation is then output on the STAT pin:
STAT = OR (Reg00[5,2:0] AND Reg01[5,2:0]) (1)
or expanded:
STAT = (UNLOCK AND x[5]) OR
(LOCK AND x[2]) OR
(THI AND x[1]) OR
(TLO AND x[0])
For example, if the application requires STAT to go high
whenever the LOCK or THI flags are set, then x[2] and
x[1] should be set to “1”, giving a register value of h6.
Block Power-Down Control
The LTC6945’s power-down control bits are located in
register h02, described in Table 9. Different portions of the
device may be powered down independently. Care must
be taken with the LSB of the register, the POR (power-on
reset) bit. When written to a “1”, this bit forces a full reset
of the part’s digital circuitry to its power-up default state.
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