LTC6945 View Datasheet(PDF) - Linear Technology
Part Name
Description
MFG CO.
'LTC6945' PDF : 28 Pages View PDF
LTC6945
APPLICATIONS INFORMATION
The next step in the algorithm is to determine the open-
loop bandwidth. BW should be at least 10× smaller than
fPFD. Wider loop bandwidths could have lower integrated
phase noise, depending on the VCO phase noise signature,
while narrower bandwidths will likely have lower spurious
power. Use a factor of 25 for this design:
BW = 250kHz = 10kHz
25
Loop Filter Component Selection
Now set loop filter resistor RZ and charge pump current
ICP. Because the KVCO varies over the VCO’s frequency
range, using the KVCO geometric mean gives good results.
Using an ICP of 11.2mA, RZ is determined:
KVCO = 106 • 15 • 21.6 = 18MHz / V
RZ
=
2
• π • 10k
11.2m •
• 3656
18M
RZ = 1.14k
Now calculate CI and CP from Equations 7 and 8:
CI
=
2
•
π
•
3.5
10k •
1.14k
=
48.9nF
CP
=
7
•
π
•
1
10k
•
1.14k
=
3.99nF
Status Output Programming
This example will use the STAT pin to monitor a phase
lock condition. Program x[2] = 1 to force the STAT pin
high whenever the LOCK bit asserts:
Reg01 = h04
Power Register Programming
For correct PLL operation all internal blocks should be
enabled, but PDREFO should be set if the REFO pin is
not being used. OMUTE may remain asserted (or the
MUTE pin held low) until programming is complete. For
PDREFO = 1 and OMUTE = 1:
Reg02 = h0A
Divider Programming
Program registers Reg03 to Reg06 with the previously
determined R and N divider values:
Reg03 = h01
Reg04 = h90
Reg05 = h0E
Reg06 = h48
Reference Input Settings and Output Divider
Programming
From Table 1, FILT = 0 for a 100MHz reference frequency.
Next, convert 7dBm into VP-P. For a CW tone, use the
following equation with R = 50:
VP-P ≅ R • 10(dBm –21)/20
(9)
This gives VP-P = 1.41V, and, according to Table 2, set
BST = 1.
Now program Reg08, assuming maximum RF± output
power (RFO[1:0] = 3 according to Table 7) and OD[2:0] = 1:
Reg08 = h99
Lock Detect and Charge Pump Current Programming
Next determine the lock indicator window from fPFD. From
Table 3, LKWIN[1:0] = 3 for a tLWW of 90ns. The LTC6945
will consider the loop “locked” as long as the phase
coincidence at the PFD is within 8°, as calculated below:
phase = 360° • tLWW • fPFD = 360 • 90n • 250k ≅ 8°
LKWIN[1:0] may be set to a smaller value to be more
conservative. However, the inherent phase noise of the
loop could cause false “unlocks” for too small a value.
6945f
20
Share Link: 
