M41ST87WMX6TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
M41ST87WMX6TR
STMicroelectronics
'M41ST87WMX6TR' PDF : 42 Pages View PDF
Figure 8. Bus Timing Requirements Sequence
SDA
tBUF
SCL
P
tHD:STA
tR
tF
tHIGH
S
tLOW
tSU:DAT
tHD:DAT
M41ST87Y, M41ST87W
tHD:STA
tSU:STA
SR
tSU:STO
P
AI00589
Table 2. AC Characteristics
Symbol
Parameter(1)
Min
Max
fSCL
SCL Clock Frequency
0
400
tBUF
Time the bus must be free before a new transmission can start
1.3
tEXPD
EX to ECON Propagation Delay
M41ST87Y
10
M41ST87W
15
tF
SDA and SCL Fall Time
300
tHD:DAT(2)
Data Hold Time
0
tHD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
600
tHIGH
Clock High Period
600
tLOW
Clock Low Period
1.3
tR
SDA and SCL Rise Time
300
tSU:DAT
Data Setup Time
100
tSU:STA
START Condition Setup Time
(only relevant for a repeated start condition)
600
tSU:STO
STOP Condition Setup Time
600
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
Unit
kHz
µs
ns
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns
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