M41ST87WMX6TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
M41ST87WMX6TR
STMicroelectronics
'M41ST87WMX6TR' PDF : 42 Pages View PDF
M41ST87Y, M41ST87W
WRITE Mode
In this mode the master transmitter transmits to
the M41ST87Y/W slave receiver. Bus protocol is
shown in Figure 12., page 14. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST87Y/W slave receiver will send
an acknowledge clock to the master transmitter af-
ter it has received the slave address (see Figure
9., page 12) and again after it has received the
word address and each data byte.
Figure 12. WRITE Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
S
WORD
ADDRESS (An)
DATA n
DATA n+1
DATA n+X P
BUS ACTIVITY:
SLAVE
ADDRESS
AI00591
Figure 13. WRITE Cycle Timing: RTC & External SRAM Control Signals
EX
ECON
tEXPD
tEXPD
AI03663
14/42
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