M41ST87WMX6TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
M41ST87WMX6TR
STMicroelectronics
'M41ST87WMX6TR' PDF : 42 Pages View PDF
M41ST87Y, M41ST87W
Tamper Connect Mode Bit (TCM1 and TCM2).
This bit indicates whether the position of the exter-
nal switch selected by the user is in the Normally
Open (TCMX = '1') or Normally Closed
(TCMX = '0') position (see Figure 14., page 16 and
Figure 16., page 17).
Figure 14. Tamper Detect Connection Options
TAMPER LO
(TPMX = 0)
I.
Tamper Polarity Mode Bits (TPM1 and TPM2).
The state of this bit indicates whether the Tamper
Pin Input will be taken high (to VOUT if TPMX = '1')
or low (to VSS if TPMX = '0') during a tamper event
(see Figure 14., page 16 and Figure
16., page 17).
TAMPER HI
(TPMX = 1)
II.
NORMALLY
OPEN
(TCMX = 1)
TPIN
VOUT(1)
TPIN
III.
NORMALLY
CLOSED
(TCMX = 0)
VOUT(2)
TPIN
TCHI/TCLO = 1
1MΩ
IV.
VCC
(3)
1MΩ
TCHI/TCLO = 0
10MΩ
TCHI/TCLO = 1
VOUT (Int)
10MΩ
TCHI/TCLO = 0
Note: These options are connected to those in Table 3.
Note: 1. If the CLRXEXT Bit is set, a second Tamper to VOUT (TPM2 = '1') during tCLR will not be detected.
2. If the CLRXEXT Bit is set, a second Tamper to VOUT (TPM2 = '1') will trigger automatically.
3. Optional external resistor to VCC allows the user to bypass sampling when power is “on.”
Table 3. Tamper Detection Truth Table
Option
Mode
I
Normally Open/Tamper to GND(1)
II
Normally Open/Tamper to VOUT(1)
III
Normally Closed/Tamper to GND
IV
Normally Closed/Tamper to VOUT
Note: 1. No battery current drawn during battery back-up.
TCMX
1
1
0
0
AI07075
TPMX
0
1
0
1
16/42
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