M41ST87WMX6TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
M41ST87WMX6TR
STMicroelectronics
'M41ST87WMX6TR' PDF : 42 Pages View PDF
M41ST87Y, M41ST87W
Data Retention Mode
With valid VCC applied, the M41ST87Y/W can be
accessed as described above with READ or
WRITE Cycles. Should the supply voltage decay,
the M41ST87Y/W will automatically deselect,
write protecting itself (and any external SRAM)
when VCC falls between VPFD (max) and
VPFD (min) (see Figure 28., page 38, Table
18., page 38). This is accomplished by internally
inhibiting access to the clock registers. At this
time, the Reset pin (RST) is driven active and will
remain active until VCC returns to nominal levels.
External RAM access is inhibited in a similar man-
ner by forcing ECON to a high level. This level is
within 0.2 volts of the VBAT. ECON will remain at
this level as long as VCC remains at an out-of-tol-
erance condition. When VCC falls below the Bat-
tery Back-up Switchover Voltage (VSO), power
input is switched from the VCC pin to the battery,
and the clock registers and external SRAM are
maintained from the attached battery supply.
All outputs become high impedance. The VOUT pin
is capable of supplying 100µA (for M41ST87W) or
150µA (for M41ST87Y) of current to the attached
memory with less than 0.3 volts drop under this
condition. On power up, when VCC returns to a
nominal value, write protection continues for trec
by inhibiting ECON. The RST signal also remains
active during this time (see Figure 28., page 38).
Note: Most low power SRAMs on the market to-
day can be used with the M41ST87Y/W RTC SU-
PERVISOR. There are, however some criteria
which should be used in making the final choice of
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all oth-
er inputs to the SRAM. This allows inputs to the
M41ST87Y/W and SRAMs to be “Don’t Care”
once VCC falls below VPFD(min). The SRAM
should also guarantee data retention down to
VCC=2.0 volts. The chip enable access time must
be sufficient to meet the system needs with the
chip enable output propagation delays included. If
the SRAM includes a second chip enable pin (E2),
this pin should be tied to VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0 volts. Manufacturers
generally specify a typical condition for room tem-
perature along with a worst case condition (gener-
ally at elevated temperatures). The system level
requirements will determine the choice of which
value to use. The data retention current value of
the SRAMs can then be added to the IBAT value of
the M41ST87Y/W to determine the total current re-
quirements for data retention. The available bat-
tery capacity for the battery of your choice can
then be divided by this current to determine the
amount of data retention available.
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
Tamper Detection Circuit
The M41ST87Y/W provides two independent in-
put pins, the Tamper Pin 1 Input (TP1IN) and
Tamper Pin 2 Input (TP2IN), which can be used to
monitor two separate signals which can result in
the associated setting of the Tamper Bits (TB1
and/or TB2, in Flag Register 0Fh) if the Tamper
Enable Bits (TEB1 and/or TEB2) are enabled, for
the respective Tamper 1 or Tamper 2. The TP1IN
Pin or TP2IN Pin may be set to indicate a tamper
event has occurred by either 1) closing a switch to
ground or VOUT (Normally Open), or by 2) opening
a switch that was previously closed to ground or
VOUT (Normally Closed), depending on the state
of the TCMX Bits and the TPMX Bits in the Tamper
Register (14h and/or 15h).
Tamper Register Bits (Tamper 1 and Tamper 2)
Tamper Enable Bits (TEB1 and TEB2). When
set to a logic '1,' this bit will enable the Tamper De-
tection Circuit. This bit must be set to '0' in order to
clear the associated Tamper Bits (TBX, in 0Fh).
Note: TEBX should be reset whenever the Tamper
Detect condition is modified.
Tamper Bits (TB1 and TB2). If the TEBX Bit is
set, and a tamper condition occurs, the TBX Bit will
be set to '1.' This bit is “Read-only” and is reset
only by setting the TEBX Bit to '0.' These bits are
located in the Flags Register 0Fh.
Tamper Interrupt Enable Bits (TIE1 and TIE2).
If this bit is set to a logic '1,' the IRQ/OUT pin will
be activated when a tamper event occurs. This
function is also valid in battery back-up if the ABE
Bit (Alarm in Battery Back-up) is also set to '1' (see
Figure 15., page 17).
Note: In order to avoid an inadvertent activation of
the IRQ/OUT pin due to a prior tamper event, the
Flag Register (0Fh) should be read prior to reset-
ting the TEBX Bit.
15/42
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