DC and AC parameters
M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB
Figure 9. Asynchronous latch controlled bus read AC waveforms
A0-A18
tAVLL
VALID
tLHAX
L
tLHLL
E
G
DQ0-DQ31
tLLLH
tELLL
tGLQX
tGLQV
tLLQX
tLLQV
tEHLX
tEHQX
tEHQZ
tGHQX
GHQZ
OUTPUT
See also Page Read
AI03645
Table 17.
Symbol
Asynchronous latch controlled bus read AC characteristics
Parameter
Test condition
M58BW016
Unit
70 80
tAVLL Address Valid to Latch Enable Low
E = VIL
Min 0
0 ns
tEHLX Chip Enable High to Latch Enable Transition
Min 0
0 ns
tEHQX Chip Enable High to Output Transition
G = VIL
Min 0
0 ns
tEHQZ Chip Enable High to Output Hi-Z
G = VIL
Max 20 20 ns
tELLL Chip Enable Low to Latch Enable Low
Min 0
0 ns
tGHQX Output Enable High to Output Transition
E = VIL
Min 0
0 ns
tGHQZ Output Enable High to Output Hi-Z
E = VIL
Max 15 15 ns
tGLQV Output Enable Low to Output Valid
E = VIL
Max 25 25 ns
tGLQX Output Enable Low to Output Transition
E = VIL
Min 0
0 ns
tLHAX Latch Enable High to Address Transition
E = VIL
Min 5
5 ns
tLHLL Latch Enable High to Latch Enable Low
Min 10 10 ns
tLLLH Latch Enable Low to Latch Enable High
E = VIL
Min 10 10 ns
tLLQV Latch Enable Low to Output Valid
E = VIL, G = VIL Max 70 80 ns
tLLQX Latch Enable Low to Output Transition
E = VIL, G = VIL Min 0
0 ns
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