M95128-DW3/P View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M95128-DW3/P' PDF : 41 Pages View PDF
M95128, M95128-W, M95128-R
6
Delivery state
Delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
7
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes Low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 12 shows three devices, connected to an MCU, on a SPI bus. Only one device is
selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the
others being high impedance.
Figure 12. Bus master and memory devices on the SPI bus
R(2)
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDO
SDI
SCK
Bus Master
VSS
VCC
CQD
VCC
VSS
CQD
VCC
VSS
CQD
VCC
VSS
CS3 CS2 CS1
R(2)
SPI Memory R(2)
Device
SPI Memory R(2)
Device
S
W HOLD
S
W HOLD
SPI Memory
Device
S
W HOLD
AI12304b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
2. These pull-up resistors, R, ensure that the M95128, M95128-W, M95128-R are not selected if the Bus Master leaves the S
line in the high-impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the
same time (that is when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so
that, when all inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do
not become High at the same time, and so, that the tSHCH requirement is met).
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