M95128-DW3/P View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'M95128-DW3/P' PDF : 41 Pages View PDF
Connecting to the SPI bus
M95128, M95128-W, M95128-R
7.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
● CPOL=0, CPHA=0
● CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 13, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
● C remains at 0 for (CPOL=0, CPHA=0)
● C remains at 1 for (CPOL=1, CPHA=1)
Figure 13. SPI modes supported
CPOL CPHA
0
0
C
1
1
C
D
MSB
Q
MSB
AI01438B
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