MPC5644B View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'MPC5644B' PDF : 114 Pages View PDF
3 PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1
should be within ±100 mV of VDD_HV_B when these channels are used for ADC_1.
4 VDD_HV_ADC1 can operate at 5V condition while VDD_HV_B can operate at 3.3V provided that ADC_1 channels
coming from VDD_HV_B domain are limited in max swing as VDD_HV_B.
5 VAINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
6 During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the
end of the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC1_S depend on programming.
7 Conversion time = Bit evaluation time + Sampling time + 1 Clock cycle delay.
8 Refer to ADC conversion table for detailed calculations.
9 Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
4.18 Fast Ethernet Controller
MII signals use CMOS signal levels compatible with devices operating at 3.3 V. Signals are not TTL compatible. They follow
the CMOS electrical characteristics.
4.18.1 MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency in 2:1 mode and two times
the RX_CLK frequency in 1:1 mode.
Table 44. MII Receive Signal Timing
Spec
Characteristic
Min
Max
Unit
M1
RXD[3:0], RX_DV,
5
RX_ER to RX_CLK
setup
M2
RX_CLK to
5
RXD[3:0], RX_DV,
RX_ER hold
M3
RX_CLK pulse width
35%
high
M4
RX_CLK pulse width
35%
low
—
—
65%
65%
ns
ns
RX_CLK period
RX_CLK period
MPC5646C Microcontroller Data Sheet, Rev. 3
82
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
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