CSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
SIN
SOUT
2
4
4
10
9
First Data
First Data
Data
12
Data
3
1
Last Data
11
Last Data
Note: Numbers shown reference Table 49.
Figure 25. DSPI classic SPI timing–master, CPHA = 0
CSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
SIN
SOUT
10
9
First Data
First Data
Data
12
Data
Last Data
11
Last Data
Note: Numbers shown reference Table 49.
Figure 26. DSPI classic SPI timing–master, CPHA = 1
MPC5646C Microcontroller Data Sheet, Rev. 3
90
Preliminary—Subject to Change Without Notice
Freescale Semiconductor