4.19.2 DSPI characteristics
Table 49. DSPI timing
Spec
Characteristic
1 DSPI Cycle Time
— Internal delay between pad associated to SCK and pad
associated to CSn in master mode for CSn1->0
— Internal delay between pad associated to SCK and pad
associated to CSn in master mode for CSn1->1
2 CS to SCK Delay2
3 After SCK Delay3
4 SCK Duty Cycle
— Slave Setup Time
(SS active to SCK setup time)
— Slave Hold Time
(SS active to SCK hold time)
5 Slave Access Time
(SS active to SOUT valid)4
6 Slave SOUT Disable Time
(SS inactive to SOUT High-Z or invalid)
7 CSx to PCSS time
8 PCSS to PCSx time
Symbol
tSCK
tCSC
tASC
tCSC
tASC
tSDC
tSUSS
tHSS
tA
tDIS
tPCSC
tPASC
Min
Refer
note1
—
15
7
15
0.4 tSCK
5
10
—
—
0
0
Unit
Max
—
ns
115
ns
—
ns
—
ns
—
ns
0.6 tSCK ns
—
ns
—
ns
42
ns
25
ns
—
ns
—
ns
MPC5646C Microcontroller Data Sheet, Rev. 3
88
Preliminary—Subject to Change Without Notice
Freescale Semiconductor