Table 49. DSPI timing (continued)
Spec
Characteristic
Symbol
Min
Unit
Max
9 Data Setup Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)5
Master (MTFE = 1, CPHA = 1)
tSUI
36
5
36
36
—
ns
—
ns
—
ns
—
ns
10 Data Hold Time for Inputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)5
Master (MTFE = 1, CPHA = 1)
tHI
0
4
0
0
—
ns
—
ns
—
ns
—
ns
11 Data Valid (after SCK edge)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tSUO
—
—
—
—
12
ns
37
ns
12
ns
12
ns
12 Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
tHO
06
9.5
07
08
—
ns
—
ns
—
ns
—
ns
1 This value of this parameter is dependent upon the external device delays and the other parameters mentioned in
this table.
2 The maximum value is programmable in DSPI_CTARn [PSSCK] and DSPI_CTARn [CSSCK]. For JPC5604B, the
spec value of tCSC will be attained only if TDSPI x PSSCK x CSSCK > tCSC .
3 The maximum value is programmable in DSPI_CTARn [PASC] and DSPI_CTARn [ASC]. For JPC5604B, the spec
value of tASC will be attained only if TDSPI x PASC x ASC > tASC.
4 The parameter value is obtained from tSUSS and tSUO for slave.
5 This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b00.
6 For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 0) is 2 ns.
7 For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 0) is 2 n.
8 For DSPI1, the Data Hold Time for Outputs in Master (MTFE = 1, CPHA = 1) is 2 ns.
MPC5646C Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
89