MPC8349VVAGF View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

MFG CO.

MPC8349VVAGF

PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications

Freescale Semiconductor 

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Ethernet: Three-Speed Ethernet, MII Management

Figure 8 shows the GMII receive AC timing diagram.

G

tGRX

tGRXR

RX_CLK

RXD[7:0]

RX_DV

RX_ER

tGRXH

tGRXF

tGRDXKH

tGRDVKH

Figure 8. GMII Receive AC Timing Diagram

8.2.2 MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.2.1 MII Transmit AC Timing Specifications

Table 23 provides the MII transmit AC timing specifications.

Table 23. MII Transmit AC Timing Specifications

At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

TX_CLK clock period 10 Mbps

tMTX

—

400

—

ns

TX_CLK clock period 100 Mbps

tMTX

—

40

—

ns

TX_CLK duty cycle

tMTXH/tMTX

35

—

65

%

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

tMTKHDX

1

5

15

ns

TX_CLK data clock rise VIL(min) to VIH(max)

tMTXR

1.0

—

4.0

ns

TX_CLK data clock fall VIH(max) to VIL(min)

tMTXF

1.0

—

4.0

ns

Note:

1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing

(MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). In general, the clock reference

symbol is based on two to three letters representing the clock of a particular function. For example, the subscript of tMTX

represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

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Freescale Semiconductor

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